Will the tda1543 operate statically? - diyAudio
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Old 1st August 2006, 02:12 PM   #1
pixpop is offline pixpop  United States
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Default Will the tda1543 operate statically?

... or must it be continually clocked in order to maintain the correct output?

If you send it a pair of values, and then stop all the input clocks, will it just hold the same output value forever?
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Old 12th August 2006, 03:40 PM   #2
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Why don't you read the datasheet? Nobody here can answer your question because nobody here reads datasheets.
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Old 12th August 2006, 05:54 PM   #3
pixpop is offline pixpop  United States
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I did read the datasheet. And after reading it, I didn't have a clear answer to my question. So I thought I would try to find someone who understood it better than I do.
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Old 12th August 2006, 06:13 PM   #4
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Hi pixpop,

When I am not mistaken, the TDA1543 holds the clocked-in sample value when the input clock is stopped. The value is latched in the output latch on the first rising edge of the clock signal, after WS has gone low.

So when data is serially clocked-in and latched after WS has gone low. Stopping the clock now, the TDA1543 will hold the output value as it is stored in the output latch. In turn the output latch controls the bit switches to select the desired output current
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Old 12th August 2006, 10:24 PM   #5
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Quote:
Originally posted by -ecdesigns-
The value is latched in the output latch on the first rising edge of the clock signal, after WS has gone low. So when data is serially clocked-in and latched after WS has gone low. Stopping the clock now, the TDA1543 will hold the output value as it is stored in the output latch.
Thanks for proving my point. Why don't you read the datasheet?

At the time WS goes low, the LSB of the current sample has not been latched and it won't be latched until the next rising BCK. The datasheet is not clear on exactly when the data is transferred to the output latch but it is unlikely to be at the exact moment the LSB is latched and it certainly can't happen before that. More likely, the data is transferred to the output latch on the second BCK after the falling WS.

We can assume the TDA1543 is static because there is no mention of minimum clock frequencies, only maximums. On the other hand, there is no mention of stop-clock operation. With any stop-clock implementation, all minimum setup and hold times must be met before the clocks resume.
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