How many IC's for single RST generator?

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Why not just build it as shown? I don't believe that any sort of additional buffering is required with the small number of ic's that receive the rst signal. This design incidentally looks like it should work just fine. I haven't looked at the reference design lately, but I had thought to do much the same and have most of the same parts for my design.. I just never finished it.. LOL

Whatever you do, don't just leave them floating - they need a valid reset signal sometime just after power up to initialize.

You might take a look at some of the existing reclocking schemes available using the master clock and some 74VHC74 D flip-flops to reclock the data and sclk to the dacs.

Read up on ground as relating to the DGND and AGND issue as the best approach to tying these together isn't always intuitive. Some app notes recommend that be done right at the dacs, note also that it is not always the case that two distinctly separate grounds results in the best performance either.

There are some people on this forum who are very much more experienced than I am and will give you great advice. jockohomo would be one such individual here.

Good luck.
 
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