How to Distribute a Clock

[Ulas]

For the benefit of Guido Tent and similarly challenged forum members, here’s a distillation of my previous posts.

The first two rules of clocked circuits are:
1. Clocks are sacred.
2. Any signal that passes through combinatorial logic is not a clock.

I interpret those rules to mean: A clock is the output of an oscillator or a flipflop that is clocked by an oscillator. The flipflop can be standalone or part of a synchronous counter or latch.

Clock buffering and fanout should be done with clock drivers, not inverters. My personal fanout guidelines are: No more than two for oscillators and no more than 4 for clocks.

Match all interfaces. Don’t drive CMOS with TTL or vice versa. Where incompatible interfaces are unavoidable, use appropriate matching logic.

Above all, stick to your principles. For example, if you have good reasons for choosing 74HC logic for your design, there can be no good reason to substitute 74AC to solve a timing problem. Fix the design.

For digital audio, I start with an oscillator that is divided by a synchronous counter to give all necessary clocks. That includes the clocks for the CDP, S/PDIF receiver, digital filter, shift registers, DAC chips, etc. Everything is synchronous.

[Guido Tent]

Originally posted by Ulas
For the benefit of Guido Tent and similarly challenged forum members, here’s a distillation of my previous posts.

The first two rules of clocked circuits are:
1. Clocks are sacred.
2. Any signal that passes through combinatorial logic is not a clock.

I interpret those rules to mean: A clock is the output of an oscillator or a flipflop that is clocked by an oscillator. The flipflop can be standalone or part of a synchronous counter or latch.

Clock buffering and fanout should be done with clock drivers, not inverters. My personal fanout guidelines are: No more than two for oscillators and no more than 4 for clocks.

Match all interfaces. Don’t drive CMOS with TTL or vice versa. Where incompatible interfaces are unavoidable, use appropriate matching logic.

Above all, stick to your principles. For example, if you have good reasons for choosing 74HC logic for your design, there can be no good reason to substitute 74AC to solve a timing problem. Fix the design.

For digital audio, I start with an oscillator that is divided by a synchronous counter to give all necessary clocks. That includes the clocks for the CDP, S/PDIF receiver, digital filter, shift registers, DAC chips, etc. Everything is synchronous.

long story, short question

what clock driver would you reccomend ?

[Spartacus]

Yep, I'd be interested to hear of a recommended clock driver too.

Guido, I currently have one of your XOs driving 16x TDA1543 plus a counter directly i.e. without any buffering. First, does this risk any damage to the XO, and if not how much of a performance defecit am I looking at? I'm hoping I can live with it for a while before inserting a driver into the circuit.

Thanks.

[janneman]

Originally posted by Ulas
[snip]The first two rules of clocked circuits are:
1. Clocks are sacred.
2. Any signal that passes through combinatorial logic is not a clock.
[snip]Clock buffering and fanout should be done with clock drivers, not inverters. My personal fanout guidelines are: No more than two for oscillators and no more than 4 for clocks.

Match all interfaces. Don’t drive CMOS with TTL or vice versa. Where incompatible interfaces are unavoidable, use appropriate matching logic.

Above all, stick to your principles. For example, if you have good reasons for choosing 74HC logic for your design, there can be no good reason to substitute 74AC to solve a timing problem. Fix the design.

For digital audio, I start with an oscillator that is divided by a synchronous counter to give all necessary clocks. That includes the clocks for the CDP, S/PDIF receiver, digital filter, shift registers, DAC chips, etc. Everything is synchronous.

Interesting viewpoints. Can you elaborate on *why* this should be so? Or is it your personal opinion? Thats OK of course, but would clarify things.

Jan Didden

[Guido Tent]

Originally posted by Spartacus
Yep, I'd be interested to hear of a recommended clock driver too.

Guido, I currently have one of your XOs driving 16x TDA1543 plus a counter directly i.e. without any buffering. First, does this risk any damage to the XO, and if not how much of a performance defecit am I looking at? I'm hoping I can live with it for a while before inserting a driver into the circuit.

Thanks.

Hi,I'd say 16 pieces is a bit too heavy load. On the risk: If one or more 47 ohm resistors are in series, I'd expect the XO to keep running. The jitter increases when the load gets heavier.

I can understand you are looking for a buffer, inserting one is my advise.

best

[Fin]

Originally posted by Guido Tent

Hi,I'd say 16 pieces is a bit too heavy load. On the risk: If one or more 47 ohm resistors are in series, I'd expect the XO to keep running. The jitter increases when the load gets heavier.

I can understand you are looking for a buffer, inserting one is my advise.

best

Hi Guido

This might be a tricky question because there is a choice and probably a trade off. I will be using an XO2.5 board with the 1/2 clock output for a TDA1541A. Two of the other three outputs will be used for two flip-flops for reclocking WS and Data.

This leaves one output. Should I use it to connect to the SAA7220 filter and let that feed the SAA7210 decoder.................or is it better to find some way to feed the decoder directly??

[Guido Tent]

Originally posted by Fin



Hi Guido

This might be a tricky question because there is a choice and probably a trade off. I will be using an XO2.5 board with the 1/2 clock output for a TDA1541A. Two of the other three outputs will be used for two flip-flops for reclocking WS and Data.

This leaves one output. Should I use it to connect to the SAA7220 filter and let that feed the SAA7210 decoder.................or is it better to find some way to feed the decoder directly??

Hi Fin,

I like the reclocking !

An HC04 based buffer will do to feed both 7210 and 20, unless Mr. Ulas comes up with a practical example of a buffer circuit.

best

[Fin]

Originally posted by Guido Tent

I like the reclocking !

An HC04 based buffer will do to feed both 7210 and 20, unless Mr. Ulas comes up with a practical example of a buffer circuit.

best

Thanks Guido

Well - I was taught by the best ;-)

So - the output from the XO2.5 will be connected directly to an input of an HC04...........then the output of the HC04 should be connected to the clock inputs of the 7210 and 7220. Do I need to put some resistors in somewhere.....and what sort of values?

[Guido Tent]

Originally posted by Fin



Thanks Guido

Well - I was taught by the best ;-)

So - the output from the XO2.5 will be connected directly to an input of an HC04...........then the output of the HC04 should be connected to the clock inputs of the 7210 and 7220. Do I need to put some resistors in somewhere.....and what sort of values?

Hello Fin

I'd say from clock out to 2 HC04 buffers. Frome there with each 47 ohm in series to the SAA chips

succes

[Fin]

Hi Guido

That makes it all clear for me.

Thanx