How to Distribute a Clock

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Ulas

Banned
Joined 2003
For the benefit of Guido Tent and similarly challenged forum members, here’s a distillation of my previous posts.

The first two rules of clocked circuits are:
1. Clocks are sacred.
2. Any signal that passes through combinatorial logic is not a clock.

I interpret those rules to mean: A clock is the output of an oscillator or a flipflop that is clocked by an oscillator. The flipflop can be standalone or part of a synchronous counter or latch.

Clock buffering and fanout should be done with clock drivers, not inverters. My personal fanout guidelines are: No more than two for oscillators and no more than 4 for clocks.

Match all interfaces. Don’t drive CMOS with TTL or vice versa. Where incompatible interfaces are unavoidable, use appropriate matching logic.

Above all, stick to your principles. For example, if you have good reasons for choosing 74HC logic for your design, there can be no good reason to substitute 74AC to solve a timing problem. Fix the design.

For digital audio, I start with an oscillator that is divided by a synchronous counter to give all necessary clocks. That includes the clocks for the CDP, S/PDIF receiver, digital filter, shift registers, DAC chips, etc. Everything is synchronous.
 
G

Guido Tent

Member
Joined 2001
TentLabs.com
Ulas said:
For the benefit of Guido Tent and similarly challenged forum members, here’s a distillation of my previous posts.

The first two rules of clocked circuits are:
1. Clocks are sacred.
2. Any signal that passes through combinatorial logic is not a clock.

I interpret those rules to mean: A clock is the output of an oscillator or a flipflop that is clocked by an oscillator. The flipflop can be standalone or part of a synchronous counter or latch.

Clock buffering and fanout should be done with clock drivers, not inverters. My personal fanout guidelines are: No more than two for oscillators and no more than 4 for clocks.

Match all interfaces. Don’t drive CMOS with TTL or vice versa. Where incompatible interfaces are unavoidable, use appropriate matching logic.

Above all, stick to your principles. For example, if you have good reasons for choosing 74HC logic for your design, there can be no good reason to substitute 74AC to solve a timing problem. Fix the design.

For digital audio, I start with an oscillator that is divided by a synchronous counter to give all necessary clocks. That includes the clocks for the CDP, S/PDIF receiver, digital filter, shift registers, DAC chips, etc. Everything is synchronous.
Click to expand...

long story, short question

what clock driver would you reccomend ?
 
S

Spartacus

Member
Joined 2002
Yep, I'd be interested to hear of a recommended clock driver too.

Guido, I currently have one of your XOs driving 16x TDA1543 plus a counter directly i.e. without any buffering. First, does this risk any damage to the XO, and if not how much of a performance defecit am I looking at? I'm hoping I can live with it for a while before inserting a driver into the circuit.

Thanks.
 
jan.didden

jan.didden

AX tech editor
Joined 2002
linearaudio.net
Paid Member
Ulas said:
[snip]The first two rules of clocked circuits are:
1. Clocks are sacred.
2. Any signal that passes through combinatorial logic is not a clock.
[snip]Clock buffering and fanout should be done with clock drivers, not inverters. My personal fanout guidelines are: No more than two for oscillators and no more than 4 for clocks.

Match all interfaces. Don’t drive CMOS with TTL or vice versa. Where incompatible interfaces are unavoidable, use appropriate matching logic.

Above all, stick to your principles. For example, if you have good reasons for choosing 74HC logic for your design, there can be no good reason to substitute 74AC to solve a timing problem. Fix the design.

For digital audio, I start with an oscillator that is divided by a synchronous counter to give all necessary clocks. That includes the clocks for the CDP, S/PDIF receiver, digital filter, shift registers, DAC chips, etc. Everything is synchronous.
Click to expand...


Interesting viewpoints. Can you elaborate on *why* this should be so? Or is it your personal opinion? Thats OK of course, but would clarify things.

Jan Didden
 
G

Guido Tent

Member
Joined 2001
TentLabs.com
Spartacus said:
Yep, I'd be interested to hear of a recommended clock driver too.

Guido, I currently have one of your XOs driving 16x TDA1543 plus a counter directly i.e. without any buffering. First, does this risk any damage to the XO, and if not how much of a performance defecit am I looking at? I'm hoping I can live with it for a while before inserting a driver into the circuit.

Thanks.
Click to expand...


Hi,I'd say 16 pieces is a bit too heavy load. On the risk: If one or more 47 ohm resistors are in series, I'd expect the XO to keep running. The jitter increases when the load gets heavier.

I can understand you are looking for a buffer, inserting one is my advise.

best
 
Fin

Fin

Member
Joined 2003
Guido Tent said:

Hi,I'd say 16 pieces is a bit too heavy load. On the risk: If one or more 47 ohm resistors are in series, I'd expect the XO to keep running. The jitter increases when the load gets heavier.

I can understand you are looking for a buffer, inserting one is my advise.

best
Click to expand...


Hi Guido

This might be a tricky question because there is a choice and probably a trade off. I will be using an XO2.5 board with the 1/2 clock output for a TDA1541A. Two of the other three outputs will be used for two flip-flops for reclocking WS and Data.

This leaves one output. Should I use it to connect to the SAA7220 filter and let that feed the SAA7210 decoder.................or is it better to find some way to feed the decoder directly??
 
G

Guido Tent

Member
Joined 2001
TentLabs.com
Fin said:



Hi Guido

This might be a tricky question because there is a choice and probably a trade off. I will be using an XO2.5 board with the 1/2 clock output for a TDA1541A. Two of the other three outputs will be used for two flip-flops for reclocking WS and Data.

This leaves one output. Should I use it to connect to the SAA7220 filter and let that feed the SAA7210 decoder.................or is it better to find some way to feed the decoder directly??
Click to expand...


Hi Fin,

I like the reclocking !

An HC04 based buffer will do to feed both 7210 and 20, unless Mr. Ulas comes up with a practical example of a buffer circuit.

best
 
Fin

Fin

Member
Joined 2003
Guido Tent said:

I like the reclocking !

An HC04 based buffer will do to feed both 7210 and 20, unless Mr. Ulas comes up with a practical example of a buffer circuit.

best
Click to expand...


Thanks Guido

Well - I was taught by the best ;-)

So - the output from the XO2.5 will be connected directly to an input of an HC04...........then the output of the HC04 should be connected to the clock inputs of the 7210 and 7220. Do I need to put some resistors in somewhere.....and what sort of values?
 
G

Guido Tent

Member
Joined 2001
TentLabs.com
Fin said:



Thanks Guido

Well - I was taught by the best ;-)

So - the output from the XO2.5 will be connected directly to an input of an HC04...........then the output of the HC04 should be connected to the clock inputs of the 7210 and 7220. Do I need to put some resistors in somewhere.....and what sort of values?
Click to expand...

Hello Fin

I'd say from clock out to 2 HC04 buffers. Frome there with each 47 ohm in series to the SAA chips

succes
 
G

Guido Tent

Member
Joined 2001
TentLabs.com
Ulas said:
For the benefit of Guido Tent and similarly challenged forum members, here’s a distillation of my previous posts.

The first two rules of clocked circuits are:
1. Clocks are sacred.
2. Any signal that passes through combinatorial logic is not a clock.

I interpret those rules to mean: A clock is the output of an oscillator or a flipflop that is clocked by an oscillator. The flipflop can be standalone or part of a synchronous counter or latch.

Clock buffering and fanout should be done with clock drivers, not inverters. My personal fanout guidelines are: No more than two for oscillators and no more than 4 for clocks.

Match all interfaces. Don’t drive CMOS with TTL or vice versa. Where incompatible interfaces are unavoidable, use appropriate matching logic.

Above all, stick to your principles. For example, if you have good reasons for choosing 74HC logic for your design, there can be no good reason to substitute 74AC to solve a timing problem. Fix the design.

For digital audio, I start with an oscillator that is divided by a synchronous counter to give all necessary clocks. That includes the clocks for the CDP, S/PDIF receiver, digital filter, shift registers, DAC chips, etc. Everything is synchronous.
Click to expand...


Mr Ulas,

You moved the issue to a new (this) toppic, but many people are still waiting for your suggestions. You may not read your maial on a daily basis, but I think it is about time to come up with some practical useful information.
 
C

classd4sure

Disabled Account
Joined 2004
diyaudio.com
Hey,

I haven't seen the original thread of origine, but based on the first post in this one, who it addressed and the tone it did so with, the level of contradicting, nonsensical nature of the so called guidelines.. all I can say is "troll".

It seems to me fan out of anything should be based on source-load worst case requirements rather than blind guidelines. There's also a set fan out per logic family if I'm not mistaken, which got no mention at all here.

"Match all interfaces. Don’t drive CMOS with TTL or vice versa. Where incompatible interfaces are unavoidable, use appropriate matching logic."

So don't use glue as glue, unless you need glue, then glue it. Got it... OH hell, see rule 2.

"Above all, stick to your principles." Look at me I'm twisting context for my own amusement.

Guido if you feel like sharing your guidelines I'll be more inclined to take them seriously, but this really can't be.

Cheers,
Chris
 
G

Guido Tent

Member
Joined 2001
TentLabs.com
classd4sure said:
Hey,

I haven't seen the original thread of origine, but based on the first post in this one, who it addressed and the tone it did so with, the level of contradicting, nonsensical nature of the so called guidelines.. all I can say is "troll".

It seems to me fan out of anything should be based on source-load worst case requirements rather than blind guidelines. There's also a set fan out per logic family if I'm not mistaken, which got no mention at all here.

"Match all interfaces. Don’t drive CMOS with TTL or vice versa. Where incompatible interfaces are unavoidable, use appropriate matching logic."

So don't use glue as glue, unless you need glue, then glue it. Got it... OH hell, see rule 2.

"Above all, stick to your principles." Look at me I'm twisting context for my own amusement.

Guido if you feel like sharing your guidelines I'll be more inclined to take them seriously, but this really can't be.

Cheers,
Chris
Click to expand...


Hello Chris,

It started with comments from Mr Ulas, on our DAC design (http://www.tentlabs.com/Products/DIYDAC/DIYDAC.html), and specifically how to distribute the clock. I (and others) in turn asked Mr Ulas what would be his advise on how to distribute a clock. The post that you refer to was his reply, still not very useful, your "troll" description matches that well.

On board I'd use as little as possible buffers. HC04 type of inverters work well in my opinion, take care of layout (see guidelines on my site) and power supply (noise rejection is only 6dB) and use picogates (74HC1G126GW) rather than DIL or SO 14 package.

Feed those clocks that are realy important directly from the main oscillator, and others from buffers.

best
 
BlackCatSound

BlackCatSound

Member
Joined 2004
Ulas said:
Clock buffering and fanout should be done with clock drivers, not inverters. My personal fanout guidelines are: No more than two for oscillators and no more than 4 for clocks.

Match all interfaces. Don’t drive CMOS with TTL or vice versa. Where incompatible interfaces are unavoidable, use appropriate matching logic.
Click to expand...

What do you think is actually inside a 'clock driver' chip? Surely they are just gates, just like the output of an inverter.

Also please can you give us some examples of matching logic. I connect TTL to CMOS a lot at work so maybe I'm doing something wrong. Please enlighten me.
 
C

classd4sure

Disabled Account
Joined 2004
diyaudio.com
Also please can you give us some examples of matching logic. I connect TTL to CMOS a lot at work so maybe I'm doing something wrong. Please enlighten me.
Click to expand...

It's probably worth paying for a copy of Art of Electronics just for what they wrote on that topic alone. I haven't seen it covered that good anywhere else.

There's no real quick explanation I know of, but some glue is incompatible to be mated directly. Certain types of cmos do have TTL compatible inputs, others don't.

Thanks for the guidelines Guido. Never mind starting a new thread, but taking the argument to a whole new venue.. just have to question the motive, can't take it too seriously.

Cheers
 
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