How Not to Distribute a Clock

[Ulas]

The diyAudio archives are filled with examples of how not to do things. Guido Tent’s Tube DAC is a case study of how not to distribute a clock. (The schematics presented here were clipped and cropped from schematics of the original design as redrawn by Algar_emi.)

Clip 1

The output of the VCXO, U10, is buffered by U18A and then fanned out with four more gates in U18. The sixth gate in U18 inverts one of the fan-outs. This arrangement was standard practice with TTL logic but it is not good practice with CMOS logic.

As the low-to-high or high-to-low clock transition passes through U18A, the current drawn by the gate causes VCC to dip and GND to spike. This is called ground bounce. It is a fact of life that happens inside the chip. Bypass capacitors, series resistors, ferrites, and inductors will not make it go away.

When the inverted clock transition is leaving U18A and entering U18B, D, E, and F, VCC and GND (inside the chip) are unsettled. The reduced VCC-to-GND differential slows the transition and propagation time of the gates, and that increases jitter. Because the individual gates in the chip are not matched, the changing VCC-to-GND differential will affect the trigger point of each gate differently, thereby increasing clock skew and jitter. With four gates changing nearly simultaneously, the effects of ground bounce increase fourfold and negatively impact the performance gate U18C (/RC_CLK).

Clip 2

At first glance, the circuit formed by U5 and U4 looks like a clever reclocking scheme utilizing feedback; but looks are deceiving. The circuit doesn’t do anything except add noise and make the design look more sophisticated than it actually is. Within two clocks after power-on, the D input of Q4A is always high before every clock and the /Q output becomes a steady state zero. As a result, CLK is just inverted /RC_CLK.

Clip 3

How does inverting the output of the VCXO three times in the noisy confines of U18 and once more in the noisy confines of U5 reduce jitter and improve the quality of the bit clock?

[rfbrw]

Originally posted by Ulas

Clip 2

Until told otherwise by the designer, I remain convinced that the circuit is incorrectly drawn.

[Joseph K]

While the original schematics is indeed incorrectly drawn, I can confirm that the contents of clip2 are conforming reality, or at least the printed circuit version in my posession.

Ciao, George

[EC8010]

As drawn in Clip 2, the output signal is directly clocked by the input clock, and that has to mean that the circuit's operation is completely different depending on whether the (jittery) audio data arrives before or after the clock edge. Unless the clock has been deliberately delayed (and without jitter), that means distortion.

[Joseph K]

U5 and U4 looks like a clever reclocking scheme utilizing feedback

I think U4 & U5 does not have anything to do with feedback & reclocking.

It is simply a way of enabling / disabling R_clk in function of the presence / missing of a burst type BCKO...

Ciao, George

Ps.: and by the way BCKO is only of secondary importance in the PCM63.

[rfbrw]

Any chance of showing us the correct version ?

[Ulas]

Originally posted by Joseph K
It is simply a way of enabling / disabling R_clk in function of the presence / missing of a burst type BCKO...

Please expalin how a presence / missing BCKO burst comes about. The two inputs to the S/R are RC_CLK and BCKO. Both are derived from the VCXO. RTFM

Ps.: and by the way BCKO is only of secondary importance in the PCM63.

I know that, but to a clockmonger, jitter is all-important. According to Guido, jitter passes through the substrate of the ICs and permeates every signal. That's why he reclocks everything including the data lines. Even if he wanted to stop CLK for this imaginary BCKO burst, why does he invert it four times? BCKO contains no state information and BCKO is the same as CLK except it has a different jitter spectrum. Maybe the purpose of U4 and U5 is to introduce anti-jitter.

[rfbrw]

It is most likely that the diagram is in error and as such it seems a mite churlish to ignore this in order to lambast your bete noir of the week.
BCKO is not derived from the VCXO. It is derived from the SM5842.

[Ulas]

Originally posted by rfbrw
It is most likely that the diagram is in error and as such it seems a mite churlish to ignore this in order to lambast your bete noir of the week.
BCKO is not derived from the VCXO. It is derived from the SM5842.

The schematics I posted depict the same components and nets as the originals. The only differences are cosmetic. Knowing how much you all want to get me, don't you think I would have made sure my case was airtight?

In your rush to defend Guido, you are ignoring Joseph K who verified that my schematic matched his Tube DAC PCB!!!!

Read the datasheet. VCXO->RF_CLK->XTI->BCKO. If BCKO isn't derived from the VCXO, where does it come from?

[Ulas]

I think Guido’s Tube DAC was originally intended as a joke but nobody got it. In fact, everyone took it so seriously that Guido and his buddies had little choice but to keep it going. Here are the clues:

1) The project description, written by Marc Heijligers, MSEE, reads like a parody.

2) The original schematics obfuscate the U4/U5 no-op by using AND symbols instead of NOR symbols for the 74HC02. I have called this “error” to Guido’s attention, as have others, but he has not changed the schematics. (I used clips from Algar_emi’s schematics because he used the correct symbols, which make clear what the circuit does.)

3) Nothing in the Tube DAC design conforms to Guido’s anti-jitter manifesto. It has no pico gates; it uses multiple gates in a chip; it has a 4-layed PCB, which, most likely, has a VCC plane; it doesn’t use a snake-oil oscillator or magic VCXO; etc.

4) While the U4/U5 red herring is very clever, the rest of the circuit is crude. There are multiple/redundant inversions in important clocks, like /RC_CLK, which reclocks WCKO, the one and only signal that influences jitter in the D-to-A conversion. The reclocking occurs very close to the falling edge of BCKO, which is when WCKO, DOL, & DOR are changing. It would have been more prudent to reclock near the rising edge of BCKO, when everything is stable, and then invert the bit clock to restore the proper phase relationship before sending it to the PCM63s.

5) The project description says, "A special circuit in-between the filter and the DAC chips is used, to reclock all digital signals entering the DAC chips. This reclocking circuit is described elsewhere (clock regeneration and jitter)." but the promised description is nowhere to be found.

6) It is very unusual for an audio product to remain unchanged for six years especially after all its major components are no longer available.

But let’s give Guido the benefit of doubt. It’s possible that when the TubeDAC was finished in 2000, he didn’t know about ground bounce and hadn’t yet developed his anti-jitter manifesto. The former is unlikely because Marc Heijligers, MSEE, talks about ground bounce in the project intro.

If Guido’s manifesto is based on knowledge and experience gained since 2000, why hasn’t he updated the Tube DAC to incorporate his newfound knowledge and experience? Don’t his paying customers deserve it? Well, not if the cost of updating the design would diminish the income he receives from the 6-year old hoax. His idea of an update is to offer the same old PCB with gold-plated traces.