How Not to Distribute a Clock

[Terry Demol]

Originally posted by Ulas


The Tube DAC team was headed by a MSEE and they labored for FIVE years. In that five years why didn't anyone of them read a book on clocked circuit design or an appnote on ground bounce? After five years they should have developed a modicum of technical proficiency. Heck, starting with just a high school diploma I progressed from computer operator to system programmer in two years. In five years I was a full-fledged computer engineer and project leader. A year later I was running my own consulting company in Silicon Valley.

As we say here in Australia, Ulas, you are a legend... in you're
own lunchtime

If you’ve spent any time in this forum you have probably come across one of Guido Tent’s rants that make up the Clockmonger Manifesto. One of them goes like this: Never use a higher bandwidth then strictly necessary. Jocko Homo says the same thing. In a nutshell, it means don’t use a fast IC when a slower one will do the job. Good advice (although one clockmonger, who has since fallen from grace, says VHC sounds better than HC) and everyone agrees that AC logic should be avoided like the plague.

Embarrassed by my recent faux pas, I was reexamining the Tube DAC schematics to see if there was something else I missed. And yes, I had missed something. U4 is specified as a 74AC74. Why was that? All the other chips are 74HC so why does U4 need higher bandwidth than necessary? It seems the DAC team was hit by the GLITCH. In my previous post I only speculated about the possibility of the GLITCH because I know bad engineering when I see it.

A responsible engineer, when confronted with the GLITCH, would try to understand the root cause and fix it. A mediocre engineer simply applies a Band-Aid and hopes the problem goes away. Guido’s team used the Band-Aid approach. A faster flipflop would increase the chances the rising edge of /Q got to the NOR gate before the falling edge of /RC_CLK and avoid the GLITCH.

Let that be a lesson for you: Any signal that passes through combinatorial logic is not a clock.

Actually, that’s the second rule of clocked circuits, as I learned them. The first is:

That means; don’t mess with a clock. Don’t modify it or tweak it and certainly don’t reclock it. If the timing of a “clock” is so bad that it needs to be reclocked, than it wasn’t a clock in the first place, it was a strobe. Reclocking a strobe doesn’t make a clock; it just makes another strobe.

When Guido Tent describes his soon-to-be-released new DAC with all the reclocking he does, I just laugh. It’s too bad he never learned the basics of clocked circuit design.

Ulas,

I suggest you pull your head in. Constructive criticism here
with clear technical backing is welcomed and can only benefit us.

Destructive criticism with personal attack such as yours really
serves no purpose. You should know better.

Maybe your digital design skills are good, but certainly your people skills are a long way off.

Cheers,

Terry

[SY]

Maybe your digital design skills are good

Well, we've seen an example of those...

[tubee]

Ulas is talking.... again....
http://www.diyaudio.com/forums/showt...828#post732828

[Guido Tent]

Originally posted by Ulas


The Tube DAC team was headed by a MSEE and they labored for FIVE years. In that five years why didn't anyone of them read a book on clocked circuit design or an appnote on ground bounce? After five years they should have developed a modicum of technical proficiency. Heck, starting with just a high school diploma I progressed from computer operator to system programmer in two years. In five years I was a full-fledged computer engineer and project leader. A year later I was running my own consulting company in Silicon Valley.

If you’ve spent any time in this forum you have probably come across one of Guido Tent’s rants that make up the Clockmonger Manifesto. One of them goes like this: Never use a higher bandwidth then strictly necessary. Jocko Homo says the same thing. In a nutshell, it means don’t use a fast IC when a slower one will do the job. Good advice (although one clockmonger, who has since fallen from grace, says VHC sounds better than HC) and everyone agrees that AC logic should be avoided like the plague.

Embarrassed by my recent faux pas, I was reexamining the Tube DAC schematics to see if there was something else I missed. And yes, I had missed something. U4 is specified as a 74AC74. Why was that? All the other chips are 74HC so why does U4 need higher bandwidth than necessary? It seems the DAC team was hit by the GLITCH. In my previous post I only speculated about the possibility of the GLITCH because I know bad engineering when I see it.

A responsible engineer, when confronted with the GLITCH, would try to understand the root cause and fix it. A mediocre engineer simply applies a Band-Aid and hopes the problem goes away. Guido’s team used the Band-Aid approach. A faster flipflop would increase the chances the rising edge of /Q got to the NOR gate before the falling edge of /RC_CLK and avoid the GLITCH.

Let that be a lesson for you: Any signal that passes through combinatorial logic is not a clock.

Actually, that’s the second rule of clocked circuits, as I learned them. The first is:



That means; don’t mess with a clock. Don’t modify it or tweak it and certainly don’t reclock it. If the timing of a “clock” is so bad that it needs to be reclocked, than it wasn’t a clock in the first place, it was a strobe. Reclocking a strobe doesn’t make a clock; it just makes another strobe.

When Guido Tent describes his soon-to-be-released new DAC with all the reclocking he does, I just laugh. It’s too bad he never learned the basics of clocked circuit design.

dear all,

I feel the need to react on some issues, not at all do I need to defend.

the DAC design started because we weren't happy with existing DACs. We worked one evening every 2 weeks during about 5 years, and yes, none of all had specific experience in that area, but we learned

The schematics as on the web do work, the boards are made based on these and hundreds are sols - they all work.

On the clock distribution: A modification has been made to avoid most inverters, this modis not published on the web, but most if not all customers do know about it. the effect by the way was very subtle, the induced jitter of an inverter is not that high, when care has been taken on layout and power supply.

The AC74 is used because it is faster, we needed that because of timing issues. It is deliberately chosen as a solution, and works in all DACs, over all temperature ranges. We could have chosen other solutions, making the circuit much more complex. there is the trade off.

I know not to mess with a clock, but when wanting to drive reclockers, the fanout of a clock itself is limited, and one has to use some buffers to drive the reclockers. Reclocking obviously is required, as the clock quality put out by digital filters is lousy (jitter !), one reason to avoid them. Everyone is free to rely on the clock put out by digtal filters, I don't.

I know about groundbounce. If you have read my paper on supply decoupling, you'll see hands-on advices how to avoid most of it. In addition, I worked for Philips semiconductors on this subject, reducing on chip bounce by taking several measures in the field of layout, circuit design (flipflops, buffers) and on-chip decoupling strategies.

mr Ulas, I sense a lot of agression in the tone of your postings, could you explain your tone ?

Then finally, what would be your preferred clocking scheme ?

best

[rfbrw]

Ulas, now you've shown us all how not to do it, perhaps you can astound us with your magnum opus, the HexadeciDAC.