Question for Guido Tent

[fmak]

Guido

Does your XOs have an enable/diable pin and what are the voltage threshold? I want to replace the Epson SG51 and SG53 modules with your XO. This is in a soundcard with word clock module containing both clock and recovered clock.

[Guido Tent]

Originally posted by fmak
Guido

Does your XOs have an enable/diable pin and what are the voltage threshold? I want to replace the Epson SG51 and SG53 modules with your XO. This is in a soundcard with word clock module containing both clock and recovered clock.

Hi Fred

They don't. Swiching them off throug the power supply or tghe output (using a relais) is the only sollution I can offer

best

[mrjam]

Guido's XOs works with 5v supply. The levels are TTL

using a relais

Too much MHZs to use a relay!

I'd use a single AND gate like this:
http://www.toshiba.com/taec/componen...//164/7388.pdf

Connect the clock output to A and enable command to B. Y will output your enabled clock.

Or, if you need to choose between different clocks to be sent to a common bus, there's the three-state buffer:

http://focus.ti.com/docs/prod/folder...4ahc1g125.html
http://focus.ti.com/docs/prod/folder...4ahc1g126.html

[Guido Tent]

Originally posted by mrjam
Guido's XOs works with 5v supply. The levels are TTL




Too much MHZs to use a relay!

I'd use a single AND gate like this:
http://www.toshiba.com/taec/componen...//164/7388.pdf

Connect the clock output to A and enable command to B. Y will output your enabled clock.

Or, if you need to choose between different clocks to be sent to a common bus, there's the three-state buffer:

http://focus.ti.com/docs/prod/folder...4ahc1g125.html
http://focus.ti.com/docs/prod/folder...4ahc1g126.html

Hi

I have good experience using Nais TQ2 relais

best

[mrjam]

Hi Guido

Nice to read from you!
What about your new dac? Is it still on progress?

The TQ2 relais have good specs, but I prefer using logic gates with digital signals.

As I told you (if you remember ), my goal is to reclock different sample rates so I need to select the clock source between three XOs: 11.** , 12.** and 24.** MHz.
I'd use a 3-state single buffer which send the enabled clock to a pll input.
It has better isolation than relais (generally around 90dB min - TQ2 are around 55dB in the range 10-20MHz), is smaller and closer to the ground plane (since they are smd), really important parameters when handling rf signals! ...as you teach us!!

Let compare it with your relay!

[Guido Tent]

Originally posted by mrjam
Hi Guido

Nice to read from you!
What about your new dac? Is it still on progress?

The TQ2 relais have good specs, but I prefer using logic gates with digital signals.

As I told you (if you remember ), my goal is to reclock different sample rates so I need to select the clock source between three XOs: 11.** , 12.** and 24.** MHz.
I'd use a 3-state single buffer which send the enabled clock to a pll input.
It has better isolation than relais (generally around 90dB min - TQ2 are around 55dB in the range 10-20MHz), is smaller and closer to the ground plane (since they are smd), really important parameters when handling rf signals! ...as you teach us!!

Let compare it with your relay!

Hi Roberto,

Thanks for the feedback.

DAC: Will be available in July. Still need to make the front end (converting USD audio / SPDIF to I2S) with low jitter performance.

Relais vs gates: I know about the isolation (though I doubt abot 90dB), but adding a buffer slightly decreases the jitter performance. Remember to treat a "digital" looking waveform as analogue, as the analogue properties are of importance........

best

[Guido Tent]

Originally posted by mrjam
Hi Guido

As I told you (if you remember ), my goal is to reclock different sample rates so I need to select the clock source between three XOs: 11.** , 12.** and 24.** MHz.

forgot to add: Switch non used VCXO's off, that isolates even better !

[HpW]

Hi,

>>forgot to add: Switch non used VCXO's off, that isolates even better !

Simple build for each VCXO a power regulator with a gate for on/off (as a mute),,

Cheers

HpW

[mrjam]

Thanks HpW!
I appreciate your suggestion,

but don't warry I know how to power down a clock module!

The psu has a regulator for each section, so 3 regs for 3 clocks. The microcontroller routine reads infos about actual sample rate from the spdif receiver and consequently drives both the pnps on the adj. pins and the 3-state single gates which isolate the outputs from the clk bus.