Guido's XOs works with 5v supply. The levels are TTL
Too much MHZs to use a relay!
I'd use a single AND gate like this:
http://www.toshiba.com/taec/components2/Datasheet_Sync//164/7388.pdf
Connect the clock output to A and enable command to B. Y will output your enabled clock.
Or, if you need to choose between different clocks to be sent to a common bus, there's the three-state buffer:
http://focus.ti.com/docs/prod/folders/print/sn74ahc1g125.html
http://focus.ti.com/docs/prod/folders/print/sn74ahc1g126.html
Too much MHZs to use a relay!
I'd use a single AND gate like this:
http://www.toshiba.com/taec/components2/Datasheet_Sync//164/7388.pdf
Connect the clock output to A and enable command to B. Y will output your enabled clock.
Or, if you need to choose between different clocks to be sent to a common bus, there's the three-state buffer:
http://focus.ti.com/docs/prod/folders/print/sn74ahc1g125.html
http://focus.ti.com/docs/prod/folders/print/sn74ahc1g126.html
mrjam said:Guido's XOs works with 5v supply. The levels are TTL
Too much MHZs to use a relay!
I'd use a single AND gate like this:
http://www.toshiba.com/taec/components2/Datasheet_Sync//164/7388.pdf
Connect the clock output to A and enable command to B. Y will output your enabled clock.
Or, if you need to choose between different clocks to be sent to a common bus, there's the three-state buffer:
http://focus.ti.com/docs/prod/folders/print/sn74ahc1g125.html
http://focus.ti.com/docs/prod/folders/print/sn74ahc1g126.html
Hi
I have good experience using Nais TQ2 relais
best
Hi Guido
Nice to read from you!
What about your new dac? Is it still on progress?
The TQ2 relais have good specs, but I prefer using logic gates with digital signals.
As I told you (if you remember
), my goal is to reclock different sample rates so I need to select the clock source between three XOs: 11.** , 12.** and 24.** MHz.
I'd use a 3-state single buffer which send the enabled clock to a pll input.
It has better isolation than relais (generally around 90dB min - TQ2 are around 55dB in the range 10-20MHz), is smaller and closer to the ground plane (since they are smd), really important parameters when handling rf signals! ...as you teach us!!
Let compare it with your relay!
Nice to read from you!
What about your new dac? Is it still on progress?
The TQ2 relais have good specs, but I prefer using logic gates with digital signals.
As I told you (if you remember
), my goal is to reclock different sample rates so I need to select the clock source between three XOs: 11.** , 12.** and 24.** MHz. I'd use a 3-state single buffer which send the enabled clock to a pll input.
It has better isolation than relais (generally around 90dB min - TQ2 are around 55dB in the range 10-20MHz), is smaller and closer to the ground plane (since they are smd), really important parameters when handling rf signals! ...as you teach us!!
Let compare it with your relay!
mrjam said:Hi Guido
Nice to read from you!
What about your new dac? Is it still on progress?
The TQ2 relais have good specs, but I prefer using logic gates with digital signals.
As I told you (if you remember
I'd use a 3-state single buffer which send the enabled clock to a pll input.
It has better isolation than relais (generally around 90dB min - TQ2 are around 55dB in the range 10-20MHz), is smaller and closer to the ground plane (since they are smd), really important parameters when handling rf signals! ...as you teach us!!
Let compare it with your relay!
Hi Roberto,
Thanks for the feedback.
DAC: Will be available in July. Still need to make the front end (converting USD audio / SPDIF to I2S) with low jitter performance.
Relais vs gates: I know about the isolation (though I doubt abot 90dB), but adding a buffer slightly decreases the jitter performance. Remember to treat a "digital" looking waveform as analogue, as the analogue properties are of importance........
best
Thanks HpW!
I appreciate your suggestion,
but don't warry I know how to power down a clock module!
The psu has a regulator for each section, so 3 regs for 3 clocks. The microcontroller routine reads infos about actual sample rate from the spdif receiver and consequently drives both the pnps on the adj. pins and the 3-state single gates which isolate the outputs from the clk bus.
I appreciate your suggestion,
but don't warry I know how to power down a clock module! The psu has a regulator for each section, so 3 regs for 3 clocks. The microcontroller routine reads infos about actual sample rate from the spdif receiver and consequently drives both the pnps on the adj. pins and the 3-state single gates which isolate the outputs from the clk bus.
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