jitter and 32bit resolution

[inatightspot]

Considering the SP/DIF format, would a DAC with 32bits of resolution allow a jitter level so low as to be without issue from the standpoint of performance and audibility?


Just curious,
Inatighspot

[HFGuy]

the number of bits has no effect on jitter. And it doesnt seem possible to create even a true 24 bit DAC as the thermal noise is greater then the lowest quantization level.

[phn]

Maybe this helps:

Jitter is a typical time distortion phenomenon, but can be studied even in the frequency domain (in this case it is properly named phase noise): in practice jitter makes side bands appear beside the fundamental. Analysis of these side bands can be used in quantifying the jitter amount.

The formula for jitter not to cause an error greater than half bit in a n bit system with f maximum signal frequency should be

Max jitter = 2 EXP -n / (pi * f)

(Note: I found the formula in a collection of old e-mails about jitter from newsgroup rec.audio.high-end. It was said it came from an AD manual, but trying to find out how it was computed I found a value four times lower...)

This formula gives 242ps as maximum jitter for a 20kHz / 16bit system. Obviously for an higher number of bits the allowed jitter decreases rapidly, reaching values critical for current technology already for 20kHz / 20 bits. Imagine what happens for 96kHz 24 bits.

Axed from TNT Audio

[HFGuy]

Originally posted by phn
Maybe this helps:

in practice jitter makes side bands appear beside the fundamental.

The formula for jitter not to cause an error greater than half bit in a n bit system with f maximum signal frequency should be

Max jitter = 2 EXP -n / (pi * f)

Axed from TNT Audio

The sidesband beside the carrier is refered to as "skirting". That formula is alittle misleading. The bit resolution doesnt really have a direct relationship to the jitter. The reason the bit resolution is in the formula is because it is being used to calculate the bit rate. A higher bit rate will require a higher transmission frequency. A higher transmission frequency will mean a lower period that a "0" or "1" (in a 2 PAM system) will be required to be read by the receiver. As an example lets assume your period is 500ps, if your jitter is 100ps then the total time the bit can be read reliable is 300ps (jitter occurs on the rising and falling edge).

As a side note the circuits i work with a jitter of less then 1ps (peak to peak , not RMS) are the normal. On the receiver side of the transmission scheme we use a phase picking or phase tracking system to locate the edge of the built in clock of the data stream. The receiver doesnt have its own clock, it recovers the clock from the data being sent. Iam surprised that in we havnt seen DACs with Clock and data recovery circuits, this would all but eliminate the jitter from the playback scheme. The only jitter would be from the differences in the clocks of the ADC that recorded the music and the DAC that will decode it.

[phn]

Ah, jitter. Can't live with it.

SACD looks better and better.

[Petter]

Originally posted by HFGuy



[snip] Iam surprised that in we havnt seen DACs with Clock and data recovery circuits, this would all but eliminate the jitter from the playback scheme. The only jitter would be from the differences in the clocks of the ADC that recorded the music and the DAC that will decode it.

[end snip]

Can you provide us with some references? I am mostly interested in stuff which I can use to try to build someting like this myself, or modules which can be purchased for inclusion in a DAC system.

Petter

[HFGuy]

IEEE Explore or a Razavi B. book is a good start . This was my area of study for the last 2 years. I worked on PLLs that operated at multi Ghz range for use in CDR systems. Using a CDR in a PCM audio system is really overkill and for the most part is pointless, but it would be a great marketing feature.

[rfbrw]

Originally posted by HFGuy



Iam surprised that in we havnt seen DACs with Clock and data recovery circuits, this would all but eliminate the jitter from the playback scheme.

Good idea. For example, if you had a dac consisting of a CS8412 and a TDA1545, you could embed data in serial clock to create one datastream and embed L/R clock in serial clock to create a second datastream and then 16B/20B encode the first and NRZ encode the second and along with serial clock transmit the lot by LVDS. At the TDA1545, nearly 5cm from the CS8412, you decode the two datastreams using CDR techniques leaving you L/R clock, data and three copies of serial clock which you then apply to a majority voting scheme.
Needless to say, the unsophisticated might consider this a little excessive but as an audiophile one knows better.