Looking at jitter with a ‘scope.

[Ulas]

[I had a windfall last year when Warner Bros used my house for a movie location. With the booty I bought a new ‘scope, an Agilent DSO6034A, with the 8M memory option, to replace a Philips PM3214. Happiness is a good ‘scope: I’m seeing things I’ve never been able to see before.]

A well-known clockmonger says you can’t see jitter with a ‘scope. Don’t believe it! Clock jitter is easily viewable, especially when it’s as gross as the output of the CS8414 in the Lite DAC-AH I have. I don’t know how anybody can call the TDA1543 a good sounding DAC chip. It does make an ideal DIY project because no matter what you do to it you can’t make it sound any worse.

In the photo, the ‘scope is triggered on the falling edge of WS and displays the first BCK rising edge after the trigger. That is assumed to be the moment when the TDA1543 changes the analog output to reflect the value of the most recent digital sample. (The TDA1453 datasheet doesn't say exactly when the converted sample appears. My assumption is based on the published behavior of the TDA1541A and TDA1545A. The conversion can’t occur any earlier, such as at the falling edge of WS, because the LSB has not been latched at that point.) The red area is the sum of the most recent traces. The gray area is the sum of all traces. In effect, the width of the red is the RMS jitter and the gray is peak-to-peak jitter. That wavy gray trace is a glitch that happened with no correlation to any external event that I know of. Aren’t digital ‘scopes great? I would never have seen that glitch with an analog ‘scope.

To display jitter you need a reference. I choose FSYNC (WS) because it is the only likely reference that is synchronized with the S/PDIF data stream. From the CS8411/12 datasheet:

When FSYNC is generated from the data, its edges are extracted at times when the intersymbol interference is at a minimum. This provides a sample frequency clock that is as spectrally pure as the digital audio source clock for moderate length transmission lines.

When S/PDIF was created, all audio DACs had parallel interfaces. They had an input pin for each bit in the sample. A 16-bit DAC had 16 input pins. The DAC chip didn’t have a clock input; it continuously produced a current that was proportional to the magnitude of the digital data on its input pins. The input pins were driven by the output of a latch that held the current digital sample. The sample timing was determined by the signal that clocked the latch. With S/PDIF, FSYNC was the signal that clocked the latch that caused the output of the DAC to change. SCK, the embedded bit clock, was intended to shift the data bits into a shift register that fed the latch, nothing more.

The trouble with the parallel-interface was that it used a lot chips, with a lot pins, and took up a lot of PCB space. The serial-interface DAC was developed to reduce the size of the total DAC footprint. Unfortunately, most of today’s DAC chips use BCK to control the timing of the D/A conversion. Bad choice! From the CS8411/12 datasheet:

SCK falling to FSYNC delay (Master Mode) Minimum: -20ns, Maximum: +20ns

Can you say jitter?

Is it any wonder most serial-interface DACs suffer from jitter and sound like **** when controlled directly from S/PDIF? There is nothing inherently wrong with S/PDIF; it’s just the DAC chip designers picked the wrong clock. If you are going to use S/PDIF, all timing should be referenced to FSYNC, not MCK or SCK.

[BlackCatSound]

Can you look at the waveform on MCK.

Jitter is a doddle to see on a good scope with persistance like that. Something mine lacks.

[LuckyLyndy]

So, Ulas
You said:

Is it any wonder most serial-interface DACs suffer from jitter

Did any manufactures of cdp's go a different route? I would think there is someone who decided to dispense with the need for an outside DAC

Have you measured the output from a hard drive file?

I saw only two people in the past couple months sell their Art/Dio's for the Dac Ah setup.

[Guido Tent]

Originally posted by Ulas
[I had a windfall last year when Warner Bros used my house for a movie location. With the booty I bought a new ‘scope, an Agilent DSO6034A, with the 8M memory option, to replace a Philips PM3214. Happiness is a good ‘scope: I’m seeing things I’ve never been able to see before.]

A well-known clockmonger says you can’t see jitter with a ‘scope. Don’t believe it! Clock jitter is easily viewable, especially when it’s as gross as the output of the CS8414 in the Lite DAC-AH I have. I don’t know how anybody can call the TDA1543 a good sounding DAC chip. It does make an ideal DIY project because no matter what you do to it you can’t make it sound any worse.

In the photo, the ‘scope is triggered on the falling edge of WS and displays the first BCK rising edge after the trigger. That is assumed to be the moment when the TDA1543 changes the analog output to reflect the value of the most recent digital sample. (The TDA1453 datasheet doesn't say exactly when the converted sample appears. My assumption is based on the published behavior of the TDA1541A and TDA1545A. The conversion can’t occur any earlier, such as at the falling edge of WS, because the LSB has not been latched at that point.) The red area is the sum of the most recent traces. The gray area is the sum of all traces. In effect, the width of the red is the RMS jitter and the gray is peak-to-peak jitter. That wavy gray trace is a glitch that happened with no correlation to any external event that I know of. Aren’t digital ‘scopes great? I would never have seen that glitch with an analog ‘scope.

To display jitter you need a reference. I choose FSYNC (WS) because it is the only likely reference that is synchronized with the S/PDIF data stream. From the CS8411/12 datasheet:


When S/PDIF was created, all audio DACs had parallel interfaces. They had an input pin for each bit in the sample. A 16-bit DAC had 16 input pins. The DAC chip didn’t have a clock input; it continuously produced a current that was proportional to the magnitude of the digital data on its input pins. The input pins were driven by the output of a latch that held the current digital sample. The sample timing was determined by the signal that clocked the latch. With S/PDIF, FSYNC was the signal that clocked the latch that caused the output of the DAC to change. SCK, the embedded bit clock, was intended to shift the data bits into a shift register that fed the latch, nothing more.

The trouble with the parallel-interface was that it used a lot chips, with a lot pins, and took up a lot of PCB space. The serial-interface DAC was developed to reduce the size of the total DAC footprint. Unfortunately, most of today’s DAC chips use BCK to control the timing of the D/A conversion. Bad choice! From the CS8411/12 datasheet:

Can you say jitter?

Is it any wonder most serial-interface DACs suffer from jitter and sound like **** when controlled directly from S/PDIF? There is nothing inherently wrong with S/PDIF; it’s just the DAC chip designers picked the wrong clock. If you are going to use S/PDIF, all timing should be referenced to FSYNC, not MCK or SCK.

dear Mr Ulas,

I passed the 200ps jitter level a long time ago. The levels I am at, cannot be seen on a scope, and it is even harder to get spectral info from such measurements.

A solution for the messy clock from the 8412/14 input receivers has been published by us many many years ago:

http://www.tentlabs.com/Products/DIYDAC/DIYDAC.html

The problems with SPDIF can be overcome for a great deal, but it is easier and much better to use I2S, if available. And yes, I agree, the 1543 is not among the best sounding DACs.

best

[jean-paul]

Originally posted by Guido Tent

And yes, I agree, the 1543 is not among the best sounding DACs.

I guess that must be "not among the best measuring DACs". There are some different opinions on how they sound apparently.

[Guido Tent]

Originally posted by jean-paul


I guess that must be "not among the best measuring DACs". There are some different opinions on how they sound apparently.

Hi Jean Paul,

It isn't among the best measuring DACs either. Given the prise and ease of use, the 1543 is great to toy around with, but it is no true competition for other DAC chips like TDA1547, PCM63 and 1704 and AD1955.

And ofcourse, I agree on your remark on different opinions.

best

[jean-paul]

Hi Guido,

Although it might measure a lot better I really never heard any TDA1547 ( regardless in what cdplayer it is used ) sing. I would choose for TDA1543 without hesitation despite it not being my favorite DAC chip.

Horses for courses....

[Guido Tent]

Originally posted by jean-paul
Hi Guido,

Although it might measure a lot better I really never heard any TDA1547 ( regardless in what cdplayer it is used ) sing. I would choose for TDA1543 without hesitation despite it not being my favorite DAC chip.

Horses for courses....

Hi Jean Paul,

The 1547 is quite critical in terms of application, the old concept versus implementation issue. The 1543 may be more easy, and forgiving, I haven't got the amount of experience with the 1543 as I have with the 1547.

cheers

[tmblack]

Not surprise the TDA1543 measured poorly.
But how about jitter for TDA1541A?

Any other good measuring chips from Burr-Brown or AD?

Tom

[jahonen]

Originally posted by Guido Tent


I passed the 200ps jitter level a long time ago. The levels I am at, cannot be seen on a scope, and it is even harder to get spectral info from such measurements.

best

Hi Guido,

Considerably less than, say 200 fs? Thats a intrinsic jitter limit of Agilent 86100C DCA-J. The price tag might be a little steep for most of us, anyway...

Regards,
Janne