PECL in Re-Clocking circuits

[KKM]

Hi guys!

I'm first time here and would like to ask about subj. My current DAC project is based on the back (from DAC to transport) syncronization design. I plan to use the TCXO (512x) as master clock generator, 74ACT74 as divider by 2 for getting the 256x freq., 74ACT153 as clock source mux, DCD328A as clock distribution driver, 74ACT74 as final re-clocking triggers. But... thinking about PECL devices for clocking from gen. to DAC. Advantages: independing from PS fluctuation, less jitter per gate, less EMI radiation.
Disadvantages: cost (about $100 for On Semiconductor devices), tarnslation from PECL to TLL/CMOS for DAC inputs.
I've found the information (On Semiconductor, AN1672) that MC100ELT21 PECL/TTL tarnslator has jitter typically 500pS. Wow! I hope to gen much less jitter value in my design
Has anybody an expirience with PECL devices as applied to re-clocking task? Are there any real advantages of PECL over ACT for clocking?

Thank you in advance for any answers.

Sergey.

[Elso Kwak]

Hi KKM,
It can be done much more simple with asynchronous reclocking. just see this thread.
http://www.diyaudio.com/forums/showt...3672#post13672

[Fred Dieckmann]

Use of logic families with edge rates faster than needed by the design is asking for signal integrity headaches, more RFI in the circuit, and compromized sonics.

AC logic does not sound good for digtal audio. The fast edge rates
and ringing make demands on power supply decoupling and signal line termination that are tricky for even an experienced logic designer with a solid signal integrity background. AC logic was such a headache for digital designers that the IC industry
ended up designing a new class of logic after it's introduction fix the problems that AC logic created.
http://www.toshiba.com/taec/componen...de/PD_cmos.pdf
http://www.toshiba.com/taec/cgi-bin/...CategoryID=126
http://www.nalanda.nitc.ac.in/indust...b/scaa034b.pdf
http://www.nalanda.nitc.ac.in/indust...b/scla013b.pdf
I have found HC to sound better that AC for digital audio as have many others. for more on signal integrity:
http://www.sigcon.com

Been there done that,
Fred

[KKM]

Hi ELSO!

I know your design as well as your oscs.
I find the synchronized design is rather then async, but more complicated. My CD player has the sync input (384x), so just needed to add a DAC

Fred,

I understand your poit of view on the AC logic. Replacing the ACT tp HCT is just soldering task , but if I want to try the PECL, I need to be sure that it's a real advantage. May be I'll route the two independent clock paths for CMOS and PECL for finding the better result. I'm a little bit in theme about high speed logic , so tricks are not a sicret for me. By the way, the CMOS are more demand to power supply then ECL, if we want to get the better jitter. What the jitter walue you think acceptable at the input of DAC chip? And, how much jitter value will be degrade on the clock path? I'm talking about the multibit DAC.

Regards,
Sergey.

[mirlo]

jitter typically 500pS

Yeccch.

Understandable, though. ECL-to-TTL or -CMOS level converters are a bitch to design. They have to have voltage gain of at least 10 yet maintain reasonably short propagation delay.