non OS pcm1704

[hugobors]

Hello,

I red with attention the analog device application note n°207 and want to do this for 24bits 96kHz or 192kHz.

For me, it's possible to do this i2S to Burr-brown signal conversion for any frequency and word length, but wanted some expert advice....

Do someone can confirm???

Thanks
Hugues

[rfbrw]

Here be nossers Non Oversampling with PCM1704

[hugobors]

Thanks but I know this, and think that the AD application note is simplier, request less logic, and so minimal time delay in the chips.

Thanks
Hugues

[rfbrw]

Originally posted by hugobors
Thanks but I know this, and think that the AD application note is simplier, request less logic, and so minimal time delay in the chips.

Thanks
Hugues

1. The AD design is intended to work with data formatted in a form AD refer to as 'packed mode'. In this mode there is one serial clock cycle for each bit and no more. In effect the entire dataword packs the frame. Unless you have a source of 24bit packed data this design will not work. With packed I2S data the first bit in each frame is the LSB of the dataword that went before so in order to reformat the data into a form suitable for the AD dac all that was needed was to delay the LRCK/WSBD by 1 bit.
2. The delay is the same. Instead of delaying the data using a shift register, the data is loaded into the left channel dac but not converted until 16 cycles or half a frame later i.e. at the same time as the right channel data. It is called the stopped clock method.

[hugobors]

Thanks a lot......

So the best thing for me is to use the shifting method??? like in the link you posted???

Thanks
Hugues

[rfbrw]

Originally posted by hugobors
Thanks a lot......

So the best thing for me is to use the shifting method??? like in the link you posted???

Thanks
Hugues

The shifting method is a possibility as is the stopped clock method which just might use less logic.

[hugobors]

Is there a place where I can find some info on the stopped clock method ?

Thanks

[rfbrw]

The AD app note uses the stopped clock method but it is tailored a certain wordlength. The nature of the stopped clock method is such that in needs to be tailored to the individual circumstances. For example the PCM1704 would require slightly different logic when going from 16/44 to 24/96 or 24/192. This kind of thing is best designed into a small CPLD.

[hugobors]

For example the PCM1704 would require slightly different logic when going from 16/44 to 24/96 or 24/192. This kind of thing is best designed into a small CPLD.

I understand that there is a change for 16 or 24 bits but don't understand for the frequencies changing. Can you explain please???

Thanks
Hugues

[rfbrw]

Originally posted by hugobors


I understand that there is a change for 16 or 24 bits but don't understand for the frequencies changing. Can you explain please???

Thanks
Hugues

The serial clock frequency is a function of LRCLK. If LRCLK changes then the serial clock frequency changes.