non OS pcm1704

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Hello,

I red with attention the analog device application note n°207 and want to do this for 24bits 96kHz or 192kHz.

For me, it's possible to do this i2S to Burr-brown signal conversion for any frequency and word length, but wanted some expert advice....

Do someone can confirm???

Thanks
Hugues
 

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hugobors said:
Thanks but I know this, and think that the AD application note is simplier, request less logic, and so minimal time delay in the chips.

Thanks
Hugues


1. The AD design is intended to work with data formatted in a form AD refer to as 'packed mode'. In this mode there is one serial clock cycle for each bit and no more. In effect the entire dataword packs the frame. Unless you have a source of 24bit packed data this design will not work. With packed I2S data the first bit in each frame is the LSB of the dataword that went before so in order to reformat the data into a form suitable for the AD dac all that was needed was to delay the LRCK/WSBD by 1 bit.
2. The delay is the same. Instead of delaying the data using a shift register, the data is loaded into the left channel dac but not converted until 16 cycles or half a frame later i.e. at the same time as the right channel data. It is called the stopped clock method.
 
The AD app note uses the stopped clock method but it is tailored a certain wordlength. The nature of the stopped clock method is such that in needs to be tailored to the individual circumstances. For example the PCM1704 would require slightly different logic when going from 16/44 to 24/96 or 24/192. This kind of thing is best designed into a small CPLD.
 
Thanks for the reply. So if I always have the same word lenght and sck, I can do with logic. If it changes, I have to implement it with some complexer logic or simplier CPLD.

In fact I want to do this with my PC with a M-audio revolution hacked to export i2S signals, but I don't know how is the i2s signal configuration. I hope it's always 32bits word length but don't know about sck, do you know this???

Thanks a lot

Hugues
 
If it is I2S then it will meet the requirements of the I2S Bus specification. If it doesn't it will be something else. The configuration of the onboard dacs will give you an idea of the format.
You might want to consider using the shift register method. So long as the number of serial clock cycles per frame remain the same, it will cover all possible wordlength/sample rate combinations
 
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