CDP gives low output after non-os modding

[gycao]

I have a SONY CDP-750, which has CXD1125 as RF, CXD1088 AS DF, and TDA1541 as DAC. I have modded it into the non-oversampling mode. It works. But the output level (both phone and RCA jack). Any suggeston?

BTW, such modding is also works with CDP-207es, CDP-950, CDP-333esd. if you want the modding, I will tell you.

[Bernhard]

I recently bypassed DF in CDP102, 502ES and 502ESII, very easy and no problem, muting still works..

[Elso Kwak]

Originally posted by gycao
I have a SONY CDP-750, which has CXD1125 as RF, CXD1088 AS DF, and TDA1541 as DAC. I have modded it into the non-oversampling mode. It works. But the output level (both phone and RCA jack). Any suggeston?

BTW, such modding is also works with CDP-207es, CDP-950, CDP-333esd. if you want the modding, I will tell you.

wrong format before digital filter?

[rfbrw]

Did you bypass the CXD1088 by simply connecting the output of the CXD1125 to the input of the TDA1541 ?

[gycao]

Originally posted by rfbrw
Did you bypass the CXD1088 by simply connecting the output of the CXD1125 to the input of the TDA1541 ?

NO. The out lines of CXD1125 to CXD1088 were cut, CXD1088 to TDA1541 too.

To put CXD1125 into 1FS mode (non-oversampling), the pin 56 was set to low, and 57 to high.

[rfbrw]

In short the CXD1125 is connected directly to the TDA1541. This is not good.Not good at all.
The input to the CXD1088 is in the Sony format. Fixed 24 bits per channel per L/R frame with LSB justified data. LRCLK is high for the left channel, low for the right.
The TDA1541 is in the I2S format. Minimum of 16bits per channel
per L/R frame with data MSB justified to the second bitcell after a transition of LRCLK. LRCLK is low for left channel and high for the right.
In effect you are turning the sign bit and the 8 MSB's into the 9 LSB's effectively leaving you with 9bit data. To make matters worse the the sign bits are now always low meaning you have halved your signal. A low output sounds about right.
To correct this you need to invert LRCLK and delay it by 7 bits.

One more thing. You say you have put the CXD1125 into 1Fs mode suggesting it was previously oversampling. In that case, what was the CXD1088 doing?

[Jocko Homo]

I can't read this place any longer.................ciao, y'all.

Call me when all the NOSsers fall off the edge of the world.

Jcoko

[gycao]

Originally posted by rfbrw
One more thing. You say you have put the CXD1125 into 1Fs mode suggesting it was previously oversampling. In that case, what was the CXD1088 doing?

Thanks rfbrw. I can answer your question.

The CXD1125 outputs 2FS signal to CDX1088, and CXD1088 outputs 4FS. CXD1088 also does digital filtering.

CXD1125, pin 56 "H", 57 "L", 2FS;

pin 56 "L", 57 "H", 1FS.
(CXD1135 too!)

[rfbrw]

Originally posted by gycao


Thanks rfbrw. I can answer your question.

The CXD1125 outputs 2FS signal to CDX1088, and CXD1088 outputs 4FS. CXD1088 also does digital filtering.

Yielding 8Fs overall. Very strange. The TDA1541 will not support 8Fs in I2S mode.

[gycao]

Not strange. I mean CXD1088 doubles the 2FS and gives 4FS.