DIR1703 -Grumble-

[5th element]

Ive not posted for over a year I think :O Ive unfortunately been Ill and am still recovering anyway moving on.

Some of you have used the DIR and commented on it actually doing what I want it to do.

As you may remember I built a DAC around the DIR1703 and a PCM1798 from TI. This uses a 12.288 crystal to generate the clock within.

The chip has CKSEL low to operate in PLL mode.

Currently the system clock is set at 256fs via SCF0 and SCF1, BRSEL is left open. This should default to a 48khz sample frequency should the chip not be able to find anything to lock onto (I think).

I have used the DAC like this for over a year, with my creative live card which upsamples everything to 48khz, during this time the DAC performed flawlessly.

I have recently purchased a M audio revolution card which supports 24bit/96khz on the SPDIF output, hoping to upsample on the computer via foobar and use the setup in 24/96.

As the DAC was currently hardwired into 48khz I thought no problem, ill just set the system clock to 128fs and connect CSBIT to BRSEL and everything will jump into action. However nothing

BRATE0/1 go high and low to represent what sample frequency is incoming. For some reason these are permenantly stuck to display 48khz? Even when I alter BRSEL and the system clock it still always displays BRATE0 - high BRATE1 - low.

Needless to say this is all very confusing as it makes no sense whatsoever. People have commented that the DIR has worked at 32/44.1/48/96khz for them without the DIR having any problems. The only issue supposedly surrounding this receiver is its inability to relock onto the incoming digital signal should the sample frequency change mid use. Well Ive got reset hard wired so I can perform a reset should be it be needed. Well nothing works.

Im totally baffled as to why this isnt working, even when wired into 96khz the BRATE pins still get stuck on 48.

What I would like to know is what settings the succesful of you have used to get this chip to function? as I am totally lost.

[tmblack]

Your've hard wired the device to PLL for 96kHz 256fs?
Does UNOLOCk go low when the is S/PDIF data fed in?

Why do you need the crystal at all in the PLL mode?

Tom

EE

[Jocko Homo]

Because the chip does not work without it.

Anyway.......Hope your are feeling better now. I'll have to think about your DIR problem.

Jocko

[5th element]

According to the DIR1703 data sheet, to hardware select it to default to 96khz, using a 12.288 crystal I have to set the system clock to 128fs and then the CSBIT to BRSEL. So it cant work 256fs, 96 with a 12.288 crystal.

In both instances I can recall where the chip had worked as intended, both the users had used 24.576 crystals. Now im not a digital buff in the least, but can read the data sheets to know how to wire the things to make them operate, apparently the DIR1703 data sheet is a bit rubbish and this may explain why

Adding to this it appears that when operating in PLL mode it can use any of the crystals it lists in the bullet points at the start. It then creates a steady 100Mhz frequency using the first internal PLL to drive the Spact device TI have made. Then it uses the second internal PLL to create the additional clocks required for the sample frequency the Spact decoded.

Its working in I2S 24 bit too, not that it matters -.-

Crystals are cheap it may be worth trying a 24.576, the data sheep suggests it not needed at all, but whats there to loose besides a pound or two.

[Jocko Homo]

That is one of the most convoluted data sheets around, and I suspect it has tons of errors. Yes, if the crystal is cheap, it would not hurt to try.

Jocko

[5th element]

My intention for the M audio card is actually to take the I2S signal from the chip onboard and just feed it striaght into my out DAC thus totally removing the SPDIF interface. However I dont know what I2S is like over a long distance.

[5th element]

Ok ive had a closer look at the card and it seems rediculously easy to get the I2S off the board. Its as if M audio designed it that way -.- Ill have a crack at this tomorrow and see what happens. Only thing is the data stream could be any number of things left right justified or w/e. Well I guess it cant hurt to try and save from the horror of the DIR1703.

Would I2S be stable over a 1- meter cable?