Using large buffer FIFO on SPDIF fed DAC

[wa2ise]

A possible way to avoid jitter issues in a DAC box fed by a SPDIF from a CD transport: build a large enough buffer that can hold enough bits to buffer the total timing error between the clock in the DAC and the clock in the CD transport, both free running. Quartz crystals are usually about 0.005 % accurate, so the free running error between two such clocks over 75 minutes (the max length of a CD) would be about half a second (worst case if one clock is high and the other low). A 1 megabit memory chip would support this. The DAC box would have a receiving chip with a PLL to receive the incoming bits from the transport. Then these bits would feed into a dual port memory clocked in off the PLL clock, and then in turn clocked out of this dual ported memory using an independent free running low jitter clock and then fed to the DAC chips. There would be a delay of the music of about half of the size of the memory (about 3/4 second) when a CD begins, and as the CD plays either the transport or the DAC eventually fills or emptys the FIFO memory, but this shouldn't happen before the CD is over.

Anyone do something like this?

[pixpop]

Some portable players implement this, for anti skip. I wonder how hard it would be to hack into the right spot. problem is, it won't be s/pdif in a portable cdp.

[rfbrw]

Originally posted by wa2ise

Anyone do something like this?

Chord.
Genesis.
Mark Levinson.

[darkfenriz]

In Poland we say: don't fight a fly with a cannon.
I don't think you need sophisticated quartz clock. I'd rather use cascade of PLLs with gradually decreasing border frequency of loop lowpass filter. This way you will get equal mean frequencies of input and output with great jitter cancellation and reasonable size of fifo memory.
regards

[rfbrw]

Originally posted by darkfenriz
In Poland we say: don't fight a fly with a cannon.

Perhaps if you did...., well thats another story for another place.

I don't think you need sophisticated quartz clock. I'd rather use cascade of PLLs with gradually decreasing border frequency of loop lowpass filter. This way you will get equal mean frequencies of input and output with great jitter cancellation and reasonable size of fifo memory.
regards

The clock at the dac end of a FIFO is as simple at it gets, a lot simple than multiple PLLs. The other advantage of a FIFO is that it fixes one end of the chain rather than having a continuous search for equilibrium, a process, the Sith Lord for one, reckons he can hear.

[rbroer]

Originally posted by rfbrw

The clock at the dac end of a FIFO is as simple at it gets, a lot simple than multiple PLLs. The other advantage of a FIFO is that it fixes one end of the chain rather than having a continuous search for equilibrium, a process, the Sith Lord for one, reckons he can hear.

Maybe, but some of us are inputting a continuous digital input stream from mediaplayers, DVD in stead of the maximum 74 minutes of a cd The buffer will either fill up or empty completely.

And what about DVD synchronisation between sound and picture

I would love to find a custom PLL with small FIFO with 0-5V output for VCO that internally operates with variable gain;
if the error is high, the output signal to the VCO changes quickly, if the error is small, the output signal will change slowly.
So you operate sub 1Hz, but still have fast locking

[rfbrw]

Originally posted by rbroer


Maybe, but some of us are inputting a continuous digital input stream from mediaplayers, DVD in stead of the maximum 74 minutes of a cd The buffer will either fill up or empty completely.

And what about DVD synchronisation between sound and picture

These are all valid concerns and, ideally, they would be addressed by faster-than-realtime data transfer.

I would love to find a custom PLL with small FIFO with 0-5V output for VCO that internally operates with variable gain;
if the error is high, the output signal to the VCO changes quickly, if the error is small, the output signal will change slowly.
So you operate sub 1Hz, but still have fast locking

I would not be surprised to find something like that already exists.

[rbroer]

Not really a simple DIY building block for a digital secundary PLL, but it seems http://www.lavryengineering.com uses a technique in their DA's called CrystalLock.
Seems just what I want, short FIFO, but still low corner frequency.
Just wonder how they manage the 3 standard sampling frequencies ?
Switching between 3 pullable crystals ?

[davidsrsb]

FPGAs or even microcontrollers could do the FIFO and buffer management these days. Fixed output clock and a VCXO for the transport clock derived from it.