Hi,
I made a DAC by CS8414 +8xTDA1543. It works well with the internal clock. However, when I apply an external clock (11.2896Mhz) and step down by the H4040, the DAC is working for about 10sec from power on but then no music out and giving "saaa saaa" noise only. Anyone know what's the problem?
Thanks for help.
regards, Ray
I made a DAC by CS8414 +8xTDA1543. It works well with the internal clock. However, when I apply an external clock (11.2896Mhz) and step down by the H4040, the DAC is working for about 10sec from power on but then no music out and giving "saaa saaa" noise only. Anyone know what's the problem?
Thanks for help.
regards, Ray
if you have built it according to my design (see my website and download the circuit dddac1543ver22.pdf) you should have no problems...... this has been built by DIY's all over the world with great succes.
the statement on ripplecounters is far to general to make real sense. The results with reclocking speaks for it self
the statement on ripplecounters is far to general to make real sense. The results with reclocking speaks for it self
ray_ben said:
H4040 as in HEF4040, the old cmos stuff ?? Check the datasheet, 11MHz might be too much for it
Use a 74HC4040.As for using that jittery divider after a not so jittery tent clock. I agree, think reclocking with the original 11MHz would be an improvement (it's on my list for my own dac).
I gave up similar problem
I also used CS8414 and TDA1543. Reclock after CS8414 with 74VHC74 and 25MHz crystal. Only the data is clocked with reference clock (MCK of CS8414). This setup ran for almost a week without problem. Then I pulled the 25MHz (soldered) and replaced with 33MHz. No sound. Then I put back the 25MHz and came the problem. Played music for a few minutes then buzzzz...
I tried my other crystals, the problem persisted. So I gave up and just used master clock.
Hope I can learn and fix mine from this thread...
I also used CS8414 and TDA1543. Reclock after CS8414 with 74VHC74 and 25MHz crystal. Only the data is clocked with reference clock (MCK of CS8414). This setup ran for almost a week without problem. Then I pulled the 25MHz (soldered) and replaced with 33MHz. No sound. Then I put back the 25MHz and came the problem. Played music for a few minutes then buzzzz...
I tried my other crystals, the problem persisted. So I gave up and just used master clock.
Hope I can learn and fix mine from this thread...
If the timing is marginal, the load presented by 8 devices might push things over the edge but 1 device might not.
Are you sure the device is in slave mode when using the external oscillator?
BTW, having gone to the trouble of using an external oscillator, why ruin it with that ghastly 4040. It is a horrendous jitter prone device with a cummulative propagation delay between outputs.
A pair of synchronous counters like the '163 would be a much better bet.
Are you sure the device is in slave mode when using the external oscillator?
BTW, having gone to the trouble of using an external oscillator, why ruin it with that ghastly 4040. It is a horrendous jitter prone device with a cummulative propagation delay between outputs.
A pair of synchronous counters like the '163 would be a much better bet.
Using a ripple counter in an application that calls for the use of a synchronous counter is inviting trouble. The fact that any DACs using HC4040’s work at all is a matter of luck. Just read the datasheets.
Depending on the manufacturer, the HC4040 has an interstage propagation delay between 5ns (typical/best-case) and 25ns (guaranteed/worst-case). With six stages between BCK and WS, the worst-case prop delay will be 150ns. Each ‘4040 stage is clocked by the falling edge of the output of the previous stage. WC will change 150ns (worst-case) after the falling edge of BCK. Since BCK is changing state every 177ns, the rising edge of BCK will occur within 22ns of the changing WS. That violates the WS setup time spec, which is 32ns.
The DDDAC is a poor design because it cannot work with any HC4040 that is slower than average but still meets the performance specs of the manufacturer. If Doede really knew what he was doing he would have used a synchronous counter or, at least, advised his customers to use an HC4040 from selected manufacturers with specific date codes. Substituting a VHC4040, while a very poor choice for other reasons, will probably solve the immediate problem.
Depending on the manufacturer, the HC4040 has an interstage propagation delay between 5ns (typical/best-case) and 25ns (guaranteed/worst-case). With six stages between BCK and WS, the worst-case prop delay will be 150ns. Each ‘4040 stage is clocked by the falling edge of the output of the previous stage. WC will change 150ns (worst-case) after the falling edge of BCK. Since BCK is changing state every 177ns, the rising edge of BCK will occur within 22ns of the changing WS. That violates the WS setup time spec, which is 32ns.
The DDDAC is a poor design because it cannot work with any HC4040 that is slower than average but still meets the performance specs of the manufacturer. If Doede really knew what he was doing he would have used a synchronous counter or, at least, advised his customers to use an HC4040 from selected manufacturers with specific date codes. Substituting a VHC4040, while a very poor choice for other reasons, will probably solve the immediate problem.
Ulas said:
Easy to put in writing
May be an opinion, not a fact....where I come from we say : de beste stuurlui staan aan wal"
it's dutch and if you find the translation you know what I mean...
For the rest, my design sound very good, cost a fraction to build of commercial equipment, has many, many very happy builders and listeners, who listen music and do not try to listen to datasheets. You obviously has not tried this, so you should hold your horese a bit.....
Ulas,
I just remember, we went through this by email already in december 2003 You don't give up eh?
you wrote to me (bit fustraded it seemed ?) :
-------------------->
No, my friend, I am not an expert. I am still learning. That's why I study and try to understand other's designs. I carefully read the data sheets, perform min/max timing analysis, and ask questions.
You are the expert. Only an expert would confidently publish a circuit without first reading the data sheets of the parts he specified and without first building and testing the circuit. Only an expert would arrogantly refuse to answer polite questions about his circuit. Unfortunately, experts like you are a dime a dozen on the Internet and experts like you have nothing to teach beginners like me.
If you want to see my designs, look for them. I assume you can use Google. That's how I found your expert designs.
I just remember, we went through this by email already in december 2003
You don't give up eh? you wrote to me (bit fustraded it seemed ?) :
-------------------->
No, my friend, I am not an expert. I am still learning. That's why I study and try to understand other's designs. I carefully read the data sheets, perform min/max timing analysis, and ask questions.
You are the expert. Only an expert would confidently publish a circuit without first reading the data sheets of the parts he specified and without first building and testing the circuit. Only an expert would arrogantly refuse to answer polite questions about his circuit. Unfortunately, experts like you are a dime a dozen on the Internet and experts like you have nothing to teach beginners like me.
If you want to see my designs, look for them. I assume you can use Google. That's how I found your expert designs.
rfbrw said:
It does prove, though, that your suggestion that this wouldn't work is not backed by empirical evidence, rendering your implied criticism that this is bad design pretty much baseless. It works fine (isn't that the ultimate sign of a good design?) with twice the chips you feel shouldn't work. And it doesn't just work fine - it sounds better than some $$$$ DACs I was able to compare them to over time, so even if the HC4040 is less than optimum, it sure seems to be good enough to beat some big name (and big name modded-) DACs.
I have built 8 DDDACs by now, 2 with 8 chips, 6 with 16 chips, and I have never experienced any of the problems you suggest should be design-specific. All units I built use a 12 mHz Tent clock, and run just fine with or without the reclocking when wired properly. A matter of luck? I used an off the shelf counter part - who knows, maybe I am just lucky? The specs of this chip are even worse of what you assume in your math with 35ns guaranteed limit, and 17ns typical...
http://www.fairchildsemi.com/ds/MM/MM74HC4040.pdf
so something is wrong with your logic, or I am REALLY lucky that this works with 16chips, in multiple DAC builds.
I find it rather curious to have folks diss a design here based on datasheet logic without having any first hand experience, basing your criticism on problems of one person who is building an 8-chip TDA1543. Note that I don't see anywhere in this thread where ray_ben actually confirms that he is building a DDDAC design.
Peter
pburke said:
Why do you feel the need to put words in my mouth in order to dispute what I never said. I simply pointed out that if timing was marginal the load presented by 8 devices may well be enough to push things over the edge.
Well, it isn't my logic or my maths but the propagation from Clock to Q0 or Q0 to Qn varies amongst manufacturers and on supply voltages and capacitive load. Good design takes into account the potential spread in device parameters.
At no point have I 'dissed' the dddac design. The worst I can be accused of is pointing out that the '4040 is a less than optimal device and that better alternatives exist.
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