Understanding of dem reclocking

[tubee]

Hello all

I use the tda1541A with pleasure, not because its easy to implement, but for its sound. Its only sounding right when paid attention to all the parts around it, and all his 28 pins needs attention!
I am right now assembling a perfboard with 4 1541's parallel, each dac gets a delayed signal from 74/163 shift registers. A while ago i have been reading this thread:

TDA1541 DEM reclocking

for a separate oscillator on pin 16-17, and might wanna try this on 4 dacs.
Want to understand the working of H.ten Pierick's scheme,
http://www.diyaudio.com/forums/attac...amp=1046767411

so:

*What is the intention of WS in, is it triggering the dem signal or can the WS signal be omitted for dem-recock? (WS will be reclocked in my 4 dac project, with Data)
* Is the 1541 externally supplied with data-sheets recommended 200 kHz oscillator frequency, or is it overclocked with another(higher) frequency?

Thanks!

[guido]

I had a mail conversation with HtP about this. reclocking WS is not needed. Output latch clocking is done on BCK (in I2S mode).

Reclocking the 4024 is for jitter removal.

Frequency needs to be sample freq multiplied by an integer.

mvg,

Guido B

[tubee]

Thanks GuidoB

I have found a 74HCT74 here, get some other parts with it and will try it on a 1541A soon.

After good results i wonder if it could be possible to split the output of 74/74 to 4 sets of BC's to dem-clock four 1541's, or feed 4 1541's with one dem-clock schematic.

[ash_dac]

Originally posted by guido
I had a mail conversation with HtP about this. reclocking WS is not needed. Output latch clocking is done on BCK (in I2S mode).

Reclocking the 4024 is for jitter removal.

Frequency needs to be sample freq multiplied by an integer.

mvg,

Guido B

Guido,

A number of these DEM threads have been started up again....

Can I ask does the external DEM circuit improve the precision of the active divider current sources?

As I understand it these current sources will be determined by

1. the difference between the -15V, and -5V supply (-10V)
2. DEM circuit / capacitor.

If so how did you keep the -10V stable?


Kind regards,

Ashley.

[guido]

Originally posted by ash_dac



Guido,

A number of these DEM threads have been started up again....

Can I ask does the external DEM circuit improve the precision of the active divider current sources?

As I understand it these current sources will be determined by

1. the difference between the -15V, and -5V supply (-10V)
2. DEM circuit / capacitor.

If so how did you keep the -10V stable?


Kind regards,

Ashley.

Hi,

I'm not the designer, Henk is. He did some posts here some time ago, don't think he's around now.

As far as understand it, you get artifacts of the dem process into the output if the freq is not a multiple of the other clockfrequencies going into the dac.

I did not continue with my dac for a while now (did some work on a 63ki), but i'm planning to have an alw -10V reg for the -10.

Greetings,

[Fin]

A "stable" (excuse the pum) -10V difference can be achieved by making the -5V from the -15V supply, by using a +10V regulator.

[DragonMaster]

"by using a +10V regulator."

??

Shouldn't a -5v reg on the -15v line do the job?

[Fin]

Originally posted by DragonMaster


??

Shouldn't a -5v reg on the -15v line do the job?

The idea is to maintain a stable 10V difference between the -5V and -15V supplies...............not to use one as a pre regulator for the other. If the reference or ground pin of the +10V reg is fed from the -15V supply, then the output of the +10V reg will be -5V AND stabilised at a 10V difference relative to the -15V supply.

[DragonMaster]

Yes, the voltage would be in-sync but the difference between both will not necessairly be 10v.

[Fin]

Originally posted by DragonMaster
Yes, the voltage would be in-sync but the difference between both will not necessairly be 10v.

Why not?