SPDIF Output from SAA7020, SAA7000

An another solution it could be to replace the SAA7010 (demodulator), SAA7020 (Error Correction), SAA7000 (CIM, interpolation and mute control) and SAA7030 (Digital Filter), Datasheets for download about http://tube.freeweb.hu/index.html ) through
the newest Philips/NXP Digital servo and PCM processor/decoder for Compact Disc "SAA7324 M2" from the CD-Pro2LF (VAU1254/31LF) datasheet see http://www.nxp.com/acrobat_download/datasheets/SAA7324_2.pdf
But now I must create appropriate bus interfaces to the two "MAB" MCU's (for servo and operating requiremets).
I cannot guess, whether it is easier than creating a bus transforming for dig. out.
 
RS is definitely not the best place to buy but you have the right part or at least an incarnation of it. It has a number of variants none of them cheap.
The XC4003E is completely impractical for this purpose and obsolete as is the ispLSI1016 into which the circuit also fits. I only used them to prototype, a process for which, FPGA's and CPLD's are very convenient. As I said a while ago, I intend some thing a lot smaller.
Any of the smaller VQ44 CPLD (PLCC-44 is also an option)devices should do and all the players in the CPLD racket will have something suitable and cheap. But you can still use 74 series TTL, if you want a Jamma board.

A more useful response to Phimor's question.

7 inverters
5 4bit synchronous counters
3 8bit shift registers
3 D-type flip-flops
1 D-type flip-flop with asynchronous clear
1 2-to-1 multiplexer
1 2-input nand gate
1 5-input and gate

That was a few years, a different CPLD logic family and software and many hard drives ago. I lost interest in that stuff a long time ago. In the unlikely event that I still have schematic, finding the software to read the file will be difficult.

I assumed that at the first "real life" test were used to real TTL ICs ( "Glue Logic") as listed above. If the first try was already perform with a CLPD, it is clear, that no schematic exist with the mentioned known TTL types.
Do you know about cad software about simulation of target funktion? So I could put in the start timing float chart and the wanted timing float chart - and an appropriate cad software supplies me the TTL glue logic circuit.
 
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Quote 3rd April 2007, 04:21 AM #55 rfbrw
Having once managed to get the CS8402A to work with the SAA7000, I have to seriously question whether it is worth the effort. Whilst all the spdif flags did what they were supposed to and there were no clicks and pops, the resulting sound was so unrelentingly bad, I had to conclude something must be wrong somewhere. Either that or the SAA7000 is not good without the SAA7030 and TDA1540.


At the weekend I discuss with a friend about reasons for your observed results. He said, the main reason was the not present, carefully developed re-clocking unit close by the DAC-IC. for low jitter this step is important, in general. By the CD-DAC Set Karik/Numerik from the British brand "Linn" this step can been selected for additional enhance of the sonic quality, especially by very large lenght of digital connection. If I realize this step, the master clock was created in the DAC and an additional digital wire to the cd player for transport of the MCK signal must be connected. By distance more than 2 m the different in sonic quality was clearly audible

When you work with the same principle, you must get nearest perfect sound quality - see post 72 about
http://www.diyaudio.com/forums/showthread.php?t=92037&page=8
 
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That kind of scheme is like icing on a cake. It can make a good design better but won't make a bad design good and there plenty of good dacs that get by without reclocking. But that does not really apply here. If what comes down the SPDIF link is wrong no amount of reclocking will correct it.
 
I've been looking at doing something like this for a while, as I've got a couple of players that use the SAA70x0 chipset. It looks like there's quite a bit of interest, so here's what I'm looking at, a PCB with:

- An IDC header with a DIP IC replacement connector that would replace the SAA7030 IC in the player.
- A Xilinx XC9572 CPLD in a PLCC44 package. This would transform the non standard digital format of the SAA7000 into MSB first right justified*. The CLOX line is divided to form the BCK line, DRCF is delayed by 24 bits and multiplexed with DLCF to form the DATA line. A 24 bit counter is triggered by the start of a clock burst on the CLCF line to form the WCK line.
- A CS8402 or CS8406 S/P DIF transmitter. If anyone can suggest a better TX that does not require a microcontroller, please speak up.
- TOSLink and transformer coupled S/P DIF output circuits.

So that's the plan, any ideas, suggestions etc?

* I would make it I2S, but it's a pain to get the serial data into a 64 bit frame. Does I2S have to have a 64 bit frame? I've always seen it like that (apart from the CD-Pro), but I couldn't find anything in the spec.
 
The DIT4096 is half the price of a CS8406 from the supplier I was going to use, so I suppose that's enough of a reason by itself. Is it actually much better?

I realised today that I had been laboring under the impression that I could use the SAA70x0 chipset's master clock to drive the S/P DIF transmitter, which of course I can't. As such, the board will need to include a clock generator. I intend to use a 16.9344MHz XO, directly clocking the TX and clocking the chipset through a divide by four circuit implemented in the CPLD. No big deal, but it does add expense.

I've attached the block diagram of my proposed design as it stands.
 

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  • SAA70x0 SPDIF TX.jpg
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Hi all.

A long shot:
Instead of trying to interface with (or replace) the circuits in the middle of the non-cooperative signal route, would it be possible to grab the signals at the DAC inputs instead?

It would be an oversampled 14-bit signal, but it's still a representation of the desired 16-bit signal, and perhaps it could be reshaped to *almost* the correct 16-bit 44.1 kHz signal that could then be output via SPDIF?

Just a thought. :)