pll1707 clock buffer

[flux01]

I'm using a PLL1707 in a DAC design, where the PLL output goes to an ASRC and a DAC. The PLL1707 datasheet recommends using an output buffer. Searching through previous posts there I've seen people using several different chips for this role (ie: a CDCVF25081 or a SN74AUC1G240). I've also seen schematics where no buffer has been used. I'm hesitant to use a buffer if none is needed, but I also have no idea what the driving capability of a PLL1707 is. It's only two ICs and relatively short traces, so I'm almost certain I don't really need a buffer, but does anyone have any thoughts on this?
Thanks,
Dave

[Rocky]

Why do you use a PLL with an async reclocker?

[flux01]

The topology is something like the one in the attached schematic. I honestly can't remember where I found this schematic, so I apologize for posting it without credit.
In any case, the topology is basically irrelevant. What I'd like to know is if anyone knows the driving capability of the PLL17xx series of PLLs.
At the moment I'm assuming they have the ability to drive two inputs and a few inches of trace. I find it hard to believe you'd need a buffer unless you were driving to another board or something like that. That being said, on more than one occasion I have been wrong, so if this is one those cases, please let me know!
Thanks,
Dave