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-   -   Digital attenuation for i2s (http://www.diyaudio.com/forums/digital-source/6152-digital-attenuation-i2s.html)

fcserei 19th September 2002 04:24 PM

Digital attenuation for i2s
 
I've succesfully connected a Philips cd player a to Behringer Ultracurve using I2s format (2*32 bits/sample) and clock sync.

The only problem the max digital output from the cd is about +6db DIGIMAX level for the behringer which overloads the EQ.
If I reduce the master level in the behringerit works fine, but I can not adjust the volume then.

I'm looking for a simple circuit or chip to attenuate the i2s signal by 12-18db with a simple bit shifting. The Behringer processes 24 bits, so shifting the input stream 2 bits seems to be no problem and Behringer shoul do something similar on the AES/EBU card, as the digit input card does not have this problem.

Can anybody help.

Steve Eddy 19th September 2002 04:41 PM

I don't understand. Are you saying that the I2S out of the CDP is sending greater than 16 bit samples?

se

fcserei 19th September 2002 04:55 PM

No. The player sends 16 bits i2s in 32 bit frames. The first 16 bit is cd data, then 16 zeros.
The behringer seems to attenuate the signal in the digital domain by 5db on the digital input (AES/EBU card), and 5db in the analog domain for the analog inputs to allow headroom for the digital eq, As I'm feeding the behringer after the A/D converters with digital signal, I have no attenuation, and overloading the eq.

What I need is a 12 db digital attenuator working with 32 bit i2s frames.

steve jones 19th September 2002 05:23 PM

Delay or shift WCLK by two bits should give you 12dB attenuation, provided that the Beringer will accept 18 bit data (or greater) .

Steve Eddy 19th September 2002 06:26 PM

Quote:

Originally posted by fcserei
No. The player sends 16 bits i2s in 32 bit frames. The first 16 bit is cd data, then 16 zeros.
Question. Where exactly are you plucking your I2S output from the CDP and how exactly are you determining that it's being sent in 32 bit frames?

The Philips I2S format is 16 bits left channel data, and 16 bits right channel data. Which decoder chip is your CDP using? And how do you you know what data format the Behringer is expecting to see out of its internal ADC?

se

fcserei 19th September 2002 08:18 PM

Quote:

Originally posted by steve jones
Delay or shift WCLK by two bits should give you 12dB attenuation, provided that the Beringer will accept 18 bit data (or greater) .
Sorry, but wrong. (Already tried - big noise).

The behringer uses 24 bits out of the 32. Let's say the input is
0011..11, after the 12dB attenuation the output with padding 0s at the end to have 24 bit data should look like 000011..11000000.

But for data beginning with 1, like 1011..11, the attenuated signal in 24 bits is 111011..11000000.


My logic design skills are a bit rusty now. Can somebody suggest a good TTL CAD package.

fcserei 19th September 2002 08:24 PM

Quote:

Originally posted by Steve Eddy


Question. Where exactly are you plucking your I2S output from the CDP and how exactly are you determining that it's being sent in 32 bit frames?

The Philips I2S format is 16 bits left channel data, and 16 bits right channel data. Which decoder chip is your CDP using? And how do you you know what data format the Behringer is expecting to see out of its internal ADC?

se

i2s does not define how long is one frame, so you can have any number of padding bits after the data. 7210 uses 32 bit frames (that is what I tap for the signal), 7220 16 bit frames, newew chips (7345) 24 bit frames.

I've checked the data sheets for A/D, D/A used in the Behringer, checked the mode config pins, and found it is communicating internally with 11.289MHz master clock, 2.822 MHz bitclock and 32 bit long frames.

guido 20th September 2002 11:19 AM

Guess you need to make a nice drawing with all the signals.
And make one MSB bit into three..

Delaying signals can be done with a '74 FF, search for Guido and you will find an I2S splitter. I use one in this design to delay WS with one clockpulse (two sides of the FF delay each half a clockpulse).

This to know where the dataframe is in time and to inverse it (not inversing the other channel).

btw, it is now designed with one 4517 shiftreg and not the 8 TTL ones. Only 3 chips left, but i have some new idea's....

Regards,

Guido

fcserei 20th September 2002 01:06 PM

Never mind, I've solved it yesterday.
A couple of D flip-flops and a multiplexer - 2 chips. Working great. It was a big help to put down exactly what I need.

Now I have about 6 dB headroom for the eq and about 16 dB usable volume adjustment. With i2s input and 20 bit filterless DAC the Behringer is in an other league now.

If anybody interested, drop me a line.
Warning: not an easy surgery.

Thanks

rfbrw 20th September 2002 09:42 PM

How do you deal with the sign bit ?

ray


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