Digital attenuation for i2s

[fcserei]

I made two shift registers out of the d flip-lfops (74..174) samling at positive edge:

a 3 stage to delay the word select (W0 is the original, W1 delayed by 1 clock cycle , W2 and W3)

a two stage to delay data (D0, D1 and D2)


The data output is always D2 except:

D0 when (W0=0 and W2=1 and W3=1) or (W0=1 and W2=0 and W3=0 )
D1 when (W0=0 and W2=0 and W3=1) or (W0=1 and W2=1 and W3=0 )

In this way I hold the sign bit for 2 more clock period then output the delayed magnitude bits.

I use a multiplexer (74..151) to make this selection. Working fine and does not alter the jitter crirical Word select.

[rfbrw]

Don't quite see how you hold the the sign bit in position and delay the other bits relative to it. For instance how many shift registers do you have in total ?

ray

[fcserei]

Originally posted by rfbrw
Don't quite see how you hold the the sign bit in position and delay the other bits relative to it. For instance how many shift registers do you have in total ?

ray

WS --> Delay ----->Delay ----->Delay ----->W2
| |
| ----------------->W1
|
----------------------------------------------->W0


Data--> Delay ----->Delay -------------------->D2
| |
| -------------------------------->D1
|
----------------------------------------------->D0

Then I use a mux co combine the signals according to the logic above.


This way the data is:

MSB MSB MSB MSB-1 MSB-2 .... LSB

instead of

MSB MSB-1 MSB-2 .... LSB

[Pulse-R]

does this mean this technique could be used to implement a 'digital volume control'?
if so, would be much easier than what I had planned...

still not quite understanding the logic though

[macboy]

does this mean this technique could be used to implement a 'digital volume control'?
if so, would be much easier than what I had planned...

Yes, but with coarse 6 dB steps. And the more attenuation you want, the more logic you need to get it. Plus the logic to select 1-of-N attentuation levels. It gets messy fast.

still not quite understanding the logic though

You need to understand the 2's complement representation of signed integers. Look it up in Wikipedia if you have to.
In 2's complement, 1 is 1, 0 is 0, etc., but -1 is "all ones", so for a 16 bit number, -1 is b11111111. Since -2 is -1 subtract 1, it is b11111110, and -3 is b11111101, etc. Note that the most significant bit becomes the sign bit (1 for negative, 0 for positive).

Consider the represention of -1 as a 12 bit number. It is b111111111111. So how do you convert an 8-bit -1 to a 12-bit -1? Well, you can't pad it with (12-8= 4) zeros, because then you get b000011111111 which is +255. And you can't just pad it with 4 ones because then a positive number becomes negative. Instead, you need to copy the sign bit 4 more times.

In fcserei's system, each channel uses a 32-bit 2's complement number per sample. The 16 MSbs are used for the 16 bit samples, with the 16 LSbs essentially unused. To attenuate the samples, he shifted the 16 bits some amount toward the LSb side (by delaying the word clock). To maintain proper 2's complement signage, he then needed to duplicate the sign bit and fill it into the 2 new MSb bits prior to the 16 bit data.

[Pulse-R]

ah, ok

yes, 6dB is a bit coarse...
back to my drawing board....
I have made a design schematic for a 16/44 - to - 24/96 converter with variable attenuator, but I am not good at PCB design... that will take longer