pcm56 questions

[BeerCan]

Hi,
In my reasearch to build a pcm56 non os dac I came accross the folowing circuit PCM56 NONOS The circuit looked simple enough for me to study.
My question has to do with the inverter (74hc04). Is this necessary? I guess I really don't understand why it is there. I know this pin on the dac has to do with the timing, but I am afraid I am lost. Could someone point me to a primer? I am really trying to understand this circuit and do not wish to just "slap parts" together.

Thanks

[wa2ise]

The line with the inverter indicates if the data is for the left channel or right channel. A low tells the DAC the data is meant for it.

[rfbrw]

The PCM56 is a mono dac and as such left and right data is expected to be in parallel with a falling edge at LE triggering conversion.
The CS8412 is a digital audio input receiver and the data is output in serial form with left or right data signified by FSYNC being high or low, depending on the chosen format.
Without the inverter you would have either left channel only or right channel only data being converted.

[BeerCan]

I see now I think. I read that in the data sheet but I did not get it. Now I see ( I think) One pcm56 needs to have its le set high and one set low otherwise I will just get single channel output. Basically data with the most significant bit first is RC and data with most significant bit last is LC.

Now as I see it wont that inverter introduce a delay in that one side? I realize it would be a small delay and probably academic, but it will be there right? If the delay is significant how would one compensate for it? I guess the obvious answer is to introduce a delay to the other dac.

Thanks again

[rfbrw]

Originally posted by BeerCan
I see now I think. I read that in the data sheet but I did not get it. Now I see ( I think) One pcm56 needs to have its le set high and one set low otherwise I will just get single channel output. Basically data with the most significant bit first is RC and data with most significant bit last is LC.

No. Study the CS8412 and PCM56 datasheets.

Now as I see it wont that inverter introduce a delay in that one side? I realize it would be a small delay and probably academic, but it will be there right? If the delay is significant how would one compensate for it? I guess the obvious answer is to introduce a delay to the other dac.

Thanks again

The use of an inverter introduces a 22.7us delay but it doesn't seem to bother most and even if it does it can be removed with varying degrees of complexity

[ALP]

Hi!

http://www.y-min.or.jp/~nob/Audio/DAC/DAC03.html - is not good circuit because have phase-shifting between channels

Please look digital part of my personal DA with propertly working PCM56.

Main idea - http://www.tnt-audio.com/clinica/convertusdecdig_e.html but released on PCM56.

AP

[ALP]

Please follow this links:

http://www.zeuslab.narod.ru/images/eXTigy/Cx2_2.jpg


http://www.zeuslab.narod.ru/images/e...usDA_Cx2_1.JPG

AP

[Francis_Vaughan]

is not good circuit because have phase-shifting between channels

Perhaps you could explain why? Looks a lot like the usual issue of a single sample delay between channels (an argument that was done to death in the 80's, 8mm of air is the clue here) but that is not the same thing as a phase shift. Of course the PCM56 is a mid 80's design.

The reset of the designs are astounding. I am not sure I have ever seen such heroic efforts to cure a problem of one's own making.

[ALP]

Originally posted by Francis_Vaughan


Perhaps you could explain why?

"Orange book" standart. DAC`s both channels will be latched simultaneously.


Looks a lot like the usual issue of a single sample delay between channels (an argument that was done to death in the 80's, 8mm of air is the clue here) but that is not the same thing as a phase shift.[/QUOTE]


please, playback via http://www.y-min.or.jp/~nob/Audio/DAC/DAC03.html (or AudioNote x.1 DAC series) white (pink) noise mono phonogramm (you can find it on many test-CD`s) and you hear interesting effect

AP

[Francis_Vaughan]

"Orange book" standart. DAC`s both channels will be latched simultaneously.

Which seems to be saying what I thought. You get a one sample delay (actually to be pedantic the latching time is not the problem, but many DACs make this simultaneous with the output - which is what is in question.)

You could fix it with a simple 16 sample shift register. However it is NOT a phase shift. It is a constant delay of one sample period. This has exactly the same effect as an additional 8mm of air.

The problem with ascribing an "interesting effect" to this design is that you have not eliminated all the other vagaries of the design, and anything from Audio Note is going to be replete with those. You need to explain what a constant one sample delay in one channel will do.

The first generation CD players all had exactly the same delay - however as a result of using a single DAC and a pair of sample hold stages. Have a read of the PCM56 data sheet, it provides the schematic in all its gory glory. This goes all the way back to the CDP101.