Asyncronous reclocking of transport SPDIF output

[Dr.H]

Hi all,

Based on some discussons here, I recently tried to reclock the SPDIF output of my Rotel 855 cd player (used as a transport) using 74HC74 fed from a 66MHz clock (asynchronous)

In stock form, the Rotel uses a 74HCT08 buffer and I placed the 74hc74 between the oversampling chip and the 74HCT08.

I have noticed very small pops occasionally coming through when music is playing.

Couple of questions:
1. Is the 74HC74 in the right place, i.e. should it be AFTER the '08?
2. Transformers on digital out appear attractive because of the comon mode impedance provided. Could I place a transformer after the '08 or should I try '74 after '08, with '74 feeding the output transformer?

Thanks for any help!
Ryan

[Jocko Homo]

Why async, instead of sync?

See if the forum search function turns up any SPDIF circuits with my name. But if it doesn't:

Don't use the Q and Q_bar to make a differential signal.

Jocko

[kevinkr]

Hi Jocko,
Can you explain your comment about not using qbar and q to make a differential signal - this is exactly what the PS Audio lambda drive does on both spdif out and aes/ebu via an output transformer.

[Bricolo]

because the Q and Q/ aren't perfectly synchronised, there's a small delay

[kevinkr]

That is what I suspected, although the differences are very small compared to the period of the actual waveform. I am not sure that a high bandwidth differential driver would be much better in this regard due to delays. I think it is questionable whether most cmos logic would drive AES/EBU or even spdif well single ended (roughly 220 ohms total with series and back termination resistors on AES/EBU) through a transformer with a ratio of 1.4:1 which is why the Lambda uses differential drive with a ratio of about 3.3:1 or 4:1 .
Perhaps paralleling a couple of gates for higher output current would work somewhat better..

When the lambda worked it sounded good, few transports at or above the price surpassed it let alone equalled it.

Kevin

Edits to fix embarrassing typos.. LOL

[Dr.H]

Jocko,

Have not seen any schematics with that search, only offers of a board and some pics of a completed circuit posted by someone. Do you have a schematic you can post here?
Thanks
Ryan

[rfbrw]

If you asynchronously reclock the SPDIF datastream, I'll wager a pound to a penny that the propagation delay between q and qbar will be the least of your worries.

[kevinkr]

My question had absolutely nothing to do with the asynchronous clocking question, but rather Jocko's assertion that driving a spdif output transformer with the Q and Q_bar outputs of a flip-flop was a bad idea. I understand in theory why this is not the best thing to do, but NO one so far has furnished evidence of a superior way of accomplishing this task. Every approach has its pitfalls.

The Lambda Drive I own commits just this faux pas, and demonstrably sounds better than almost anything I have yet heard except for some very expensive teac/esoteric drives.

Kevin

[rfbrw]

Originally posted by kevinkr
My question had absolutely nothing to do with the asynchronous clocking question, but rather Jocko's assertion that driving a spdif output transformer with the Q and Q_bar outputs of a flip-flop was a bad idea. I understand in theory why this is not the best thing to do, but NO one so far has furnished evidence of a superior way of accomplishing this task. Every approach has its pitfalls.

The Lambda Drive I own commits just this faux pas, and demonstrably sounds better than almost anything I have yet heard except for some very expensive teac/esoteric drives.

Kevin

Perhaps a re-reading of the title of this thread, not to mention the first post, is in order.

[Elso Kwak]

(Asynchronous) reclocking should be done after the DIR and also after the digital filter if present IMO.