bocka said:
Transmission lines aren't lumped components. You cannot decouple frequencies above 10MHz or so (typical values: about 1nH parasitic inductance of a 0805 component and 100nF decoupling capacitor) with caps, because of its inductive component. I'm not talking about AF, I'm talking about decoupling in the 100MHz to several GHz range. Have you ever calculated/simulated the characteristic impedance of a powerplane? You'll see that the resisive component of copper (a lossy transmission line) will dampen oscillations with lowest characteristic impedance (as I've written before: less than 1 ohm!). Oh of course it depends of your substrate thickness, you will not see such effects with standard substates of 0.5mm. Schoolbooks sometimes worth to look in...
No, absolutely not!Have you ever build DDRRAM interfaces? Do it and you'll see that problems appear in audio applications are easy to handle. With datarates of more than 100MHz and harmonics above 1 GHz, cycle times in the ns and skew between clocks in the ps range a processor PCB is much more critical than audio.
I have never mentioned lumped elements, so please do me a favour and stick to the subject.
The true impedance ofcorse depends on the physical current distribution. Indeed, if you take big planes, the impedance decreases, ASSUMED ALL CURRENT DISTRIBUTES EVENLY
Practice ofcourse is different, I have measured that.
"With a characteristic impedance of 1 ohm or less powerplanes dampens any network resonance"
is what you wrote. Looks quite cheap to me to come up with resistive excuses after I remembered that you actually have to drain energy in order to damp. Additionally, the LC resonance I pointed you at is not across the plane, but between planes - hence to damp this you need parallel resistance.
Besides, I am talking copper, normally 35u. Substrates are different subject, they have higher resistances (measured, simulated and experienced that too).
In my audio projects I generate and distribute clocks with jitter far below 1 ps so I know my subject.
Anyway, we differ from approaching decoupling theory
Hi all,
An engineer friend of mine offered some advice about my DAC project that I brought up earlier in this thread. I brought up the issue of using a power plane with him. I told him what some of you guys are suggesting about power planes resonating with ground. According to him:
"What about effectively making this a second ground plane?
As this plane would have 'cuts' in in to route the regulated power traces, the purpose of this ground plane should be only to isolate sets of routing layers for reducing noise between layers. All component grounds should still go to the (original) or bottom ground plane because this is the only one that is contiguous with no slots. This is important because (as someone has posted), high-speed signal returns tend to follow the path of least *impedance* (not necessarily the path of least *resistance*) and so slots would tend to interrupt this flow."
So does the above seem a like a good approach or not? Should I have a power plane or not?
Thanks,
Stuart
An engineer friend of mine offered some advice about my DAC project that I brought up earlier in this thread. I brought up the issue of using a power plane with him. I told him what some of you guys are suggesting about power planes resonating with ground. According to him:
"What about effectively making this a second ground plane?
As this plane would have 'cuts' in in to route the regulated power traces, the purpose of this ground plane should be only to isolate sets of routing layers for reducing noise between layers. All component grounds should still go to the (original) or bottom ground plane because this is the only one that is contiguous with no slots. This is important because (as someone has posted), high-speed signal returns tend to follow the path of least *impedance* (not necessarily the path of least *resistance*) and so slots would tend to interrupt this flow."
So does the above seem a like a good approach or not? Should I have a power plane or not?
Thanks,
Stuart
If you inject a wave into your powerplane system it spread out concentric at first, it is reflected on the edges then and these waves overlays from both directions because the width is not small against the length in a typical PCB. The resistance load per unit lenght becomes much more important the lower the characteristic impedance is. That means for a very low characteristic impedance like 1 ohm or less the DC resistance of copper is not negligible small as it is at a typical characterstic impedance of 50 ohms for a coax cable. Wenn you also consider that the thickness is often reduced from 35µ to 17µ or less in multilayer boards the DC resistance dampens as well as the losses in the PCB dielectrica the topolgy resonance of a powerplane, if - and only if - both GND and Power plane come close together.
I've got the measurements of the characteristic impedance of a PCB with very low substate thickness. The measurements are very impressive with a well damped resonance in the 100MHz range. The resonance is not only damped very well, it's absolute value is also very low, lower than a typical 100nF cap at the same frequency. Such a powerplane is not a plate capacitor as it is written most often. The PCB is part of the energy storage system and dampens the wave the larger the distance is. Limitation: at high frequencies only where the wavelength is not large against the length of the PCB edges any more. At lower frequencies the PCB behave in the typical manner where current flows in loops. This also does not mean that it is not meaningfull to break the current loops for AF with ferrite beads or chokes.
I hope this makes it clearer now.
At this point I'd like to suggest we get JakaRacman, GuidoT, Boky, Bocka in the same room, and in front of a big whiteboard, with a webcam!
I thought I knew a bit about grounding... always good to see that there is someone else out there that knows more...
Good work guys! Keep it coming...
apollyon25
________________________________
Never give up the quest for knowledge!
I thought I knew a bit about grounding... always good to see that there is someone else out there that knows more...
Good work guys! Keep it coming...
apollyon25
________________________________
Never give up the quest for knowledge!
bocka said:
Hi,
We where discussing decoupling strategies, and the everlasting number of grounplanes to order at your local PCB supplier.
Since relatively small current loops are involved in average PCB design, the discussion focueed on the parasitics involved in such layout. Transmission lines of 1 ohm where not discussed there
Currents run in loops (Kirchoff). They will always run in the loop that shows the lowest impedance. In average apllications, from a few kHz onwards, the minimum flux principle comes in, e.g. the current will run in the loop showing lowest inductance. For frequencies below few kHz, the DC resistance is what counts.
I am well aware of the DC resistance of thin copper, but it usually isn't enough (in the range of ohms) to effectively dampen the LC network formed by the loop and the decoupling.
To avoid currents running where I don't want them to interact with others, I always, by sedign, force them where I want them. This way I keep the reference clean hence it behaves as an equipotential plane.
I am well aware of how currents may spread across a plane, but if you understand above philosophy, you'll understand I never encounter such waves in my systems.
best regards
Jaka Racman said:
Jacka,
In simple form this is correct. However, and I am sure you could have worked this out it is not always simple.
PCM63 for example is really a current sinking DAC. Its output is 0 to -4mA with zero output at -2mA. It has a +2mA bipolar offset current pin that can be joined to the I out pin to give 0mA at zero output.
This means for positive outputs the current isn't sourced from the +ve supply but reduced on the -ve supply.
Ground Fill
Here's a link to a nice article by Howard Johnson in EDNMAG:
http://a330.g.akamai.net/7/330/2540/20050519160734/www.edn.com/contents/images/601835.pdf
Here's a link to a nice article by Howard Johnson in EDNMAG:
http://a330.g.akamai.net/7/330/2540/20050519160734/www.edn.com/contents/images/601835.pdf
Hi Guido and all,
Guido, I have a question regarding the equipotential plane and preferred bypassing.
The way I see the bypass capacitor, which I hope should be adequate for the issue I am raising, can be modelled as a pure capacitor in series with an inductor.
Is not the bypass capacitor a two terminal device of mainly L & C?
When it comes to it's placement does it matter which side the inductor is on and which side the capacitor is on. Or in other words when it is used to bypass an IC power supply pin to the IC gnd pin does it matter whether it is near the gnd pin, power pin or any where in between.
best regards, Craig.
Guido, I have a question regarding the equipotential plane and preferred bypassing.
The way I see the bypass capacitor, which I hope should be adequate for the issue I am raising, can be modelled as a pure capacitor in series with an inductor.
Is not the bypass capacitor a two terminal device of mainly L & C?
When it comes to it's placement does it matter which side the inductor is on and which side the capacitor is on. Or in other words when it is used to bypass an IC power supply pin to the IC gnd pin does it matter whether it is near the gnd pin, power pin or any where in between.
best regards, Craig.
CraigBuckingham said:
Hello Craig,
There are 2 aspects related to your question
1) Total inductance in decoupling loop
2) Decoupling current running through the ground plane
1) This inductance mainly depends on loop area and component inductance. Loop area can be minimised by keeping the loop small and flat.
With this in mind, it doesn' matter where the cap is physically located as long as loop area is small
2) The decoupling current runs through a part of the ground plane. As such, it develops a voltage across that plane, mainly L*(di/dt) where L is the inductance of that part of the ground.
This voltage may couple into other signals and for sure will increae the RF emission caused by attached wiring .
For this reason I recommend to place the decoupling cap as close as possible to the ground (Vss) pin, hence the involved part of the plane is as small as possibe so the induced voltage remains smallest as well.
For the experience among us, you may connect the ground of the decoupling cap with a seperate trace to the ground of the IC. Unfortunately this is not well suported most modern layout software.......
I hope all helps. You may like to read it again in
http://www.tentlabs.com/Info/Articles/Supply_decoupling.pdf
all the best
Hi Guido,
Thankyou for your experience.
This paragraph agrees with what I asked and answers the question.
My other query is, in practice how well coupled magnetically are the return trace and the IC internal die bond, wire and lead frames. That is, what % of inductance cancellation can be gained?
I would imagine that it would vary with the preciseness of placement and distance. Variables such as package types and board thicknesses come to mind for the distance parameter.
regards, CB
Thankyou for your experience.
This paragraph agrees with what I asked and answers the question.
My other query is, in practice how well coupled magnetically are the return trace and the IC internal die bond, wire and lead frames. That is, what % of inductance cancellation can be gained?
I would imagine that it would vary with the preciseness of placement and distance. Variables such as package types and board thicknesses come to mind for the distance parameter.
regards, CB
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