Multilayer ground

Status
This old topic is closed. If you want to reopen this topic, contact a moderator using the "Report Post" button.
Hi Guido,
Is it possible that there are TWO approaches to I to V conversion using IC's:
1. Current feedback IC's, where I to V conversion does happen across low IC input impedance.
2. Voltage feedback IC's (FET input) where current to voltage conversion happens across feedback resistor.

Could you please check the attached file - it is about DAC applications in programmable power supplies, but there's a topic: voltage out programmable power supplies that explains I to V conversion using current out DAC's and FET input IC' - page 1, second topic.


You completely miss the point: An IV converter has ZERO (0) input impedance, after all that is what you wanted.
This is what I can not accept - there's no current running from DAC via neither inputs of the balanced transistors input pair to the ground! In my opinion this current redirects - finds lower impedance path via feedback resistor to the ground (SOMEHOW - I'M trying to understand THIS part! – and where's GAIN coming from then??)
At the steps currents flow......
This is why I try always to use very low input bias current IC's and very fast settling times - pls. go back to the attached document, same topic.
And yes, there's still semi manufacturers advising to put ferrites between both grounds. Do there guys ever measure ?
The PCB's in my DENON CD player are single - sided only! Using ferrite beads between different ground sections of very noisy, and not very noisy digital sections might be the only way to control RF interference in such a bad design. This is why I removed these beads, isolated ground sections and fed digital ground from the power supply to each section via very wide ribbons. Measuring showed huge reduction in noise, and my ears really liked it as well.

Regards,
Extreme_Boky
 
Hi,

just remember Kirchoff's first law .

Your DAC corrent flows through feedback resistor, output of opamp, opamp's power supply pin, opamp's power supply back to the ground of the power supply and ground connection between power supply ground and DAC ground connection, then again through DAC power pin, DAC's power supply and it's ground connection to the DAC's ground pin.

At least this is steady state. At transients, current also flows through parasitic capacitances, charging and discharging them.

Best regards,

Jaka Racman
 
Extreme_Boky said:
Hi Guido,
Is it possible that there are TWO approaches to I to V conversion using IC's:
1. Current feedback IC's, where I to V conversion does happen across low IC input impedance.
2. Voltage feedback IC's (FET input) where current to voltage conversion happens across feedback resistor.

in either case, what is the input impedance ?

regards
 
Extreme_Boky said:

This is what I can not accept - there's no current running from DAC via neither inputs of the balanced transistors input pair to the ground! In my opinion this current redirects - finds lower impedance path via feedback resistor to the ground (SOMEHOW - I'M trying to understand THIS part! – and where's GAIN coming from then??)

The current does not flow into the input of the opamp, but through the conversion resistor.

I propose youy apply opamp basic assumptions

No input current
Infinite gain
zero voltage between both inputs

which will increase insight in the current flow

Gain ofcourse is set by the value of the conversion R
 
I made some reflections about multilayer grounding this morning. Energy is located in the dielectrica. Refering to the links Jaka Racman has posted an optimised multilayer stack seems to me like this:

Layer 1: mounting pads top side, signal
Layer 2: GND
Layer 3: Power
Layer 4: signal
Layer 5: GND
Layer 6: mounting pads bottom side, signal

This should result in the lowest EMI for high (highest) frequency because every signal layer has an grounded return path, signal routing on both sides of the PCB is possible (refuse routing singnals on the outer sides of a PCB makes a layout much wors in many cases) and the energy storing system (power supply) is not divides by an signal layer. If the power signal pads are routed on the shortest way to the power planes it is no nessesary to locate the blocking caps close to yout ICs. I've seen this works up to several GHz with lowest EMI (but with an 12 layer PCB).

Extreme_Boky:

1. Current feedback IC's, where I to V conversion does happen across low IC input impedance.

As Jaka & Guido said: This is impossible by Kirchhoffs law. The voltage between the two input pins of an OP is zero, with I = U * R there is no current running in the OP.

But if we discuss possible high frequency return path it might be better if you use an 4 layer PCB. A 6 layer (or more) PCB is not necessarily better than a 4 layer PCB.
 
Jaka Racman said:
Hi,

just remember Kirchoff's first law .

Your DAC corrent flows through feedback resistor, output of opamp, opamp's power supply pin, opamp's power supply back to the ground of the power supply and ground connection between power supply ground and DAC ground connection, then again through DAC power pin, DAC's power supply and it's ground connection to the DAC's ground pin.

At least this is steady state. At transients, current also flows through parasitic capacitances, charging and discharging them.

Best regards,

Jaka Racman

I guess that if you are at the DAC's ground connection, you are already at the DAC's ground pin. No need to go through the DAC's power pin and PS.:xeye:

However, not all dacs return current go to DAC's ground pin. There is at least one where it is going to the pos powersupply pin :D
 
bocka said:
I
This should result in the lowest EMI for high (highest) frequency because every signal layer has an grounded return path,

the number of layer gives no guarantee upon EMI levels, it only helps to achieve them (easily).

I have consulted companies in their design work, going from 6 layers with loads of problems to 2 layers passing all EMI tests.

One should look at the currents, and avoid as much as possible that these run through significant parts of the ground plane.

An example is the placement of decoupling capacitors - the se should be as close a spossible to the ground pin of the IC being decoupled.

regards
 
bocka said:
I made some reflections about multilayer grounding this morning. Energy is located in the dielectrica. Refering to the links Jaka Racman has posted an optimised multilayer stack seems to me like this:

Layer 1: mounting pads top side, signal
Layer 2: GND
Layer 3: Power
Layer 4: signal
Layer 5: GND
Layer 6: mounting pads bottom side, signal

This should result in the lowest EMI for high (highest) frequency because every signal layer has an grounded return path, signal routing on both sides of the PCB is possible (refuse routing singnals on the outer sides of a PCB makes a layout much wors in many cases) and the energy storing system (power supply) is not divides by an signal layer. If the power signal pads are routed on the shortest way to the power planes it is no nessesary to locate the blocking caps close to yout ICs. I've seen this works up to several GHz with lowest EMI (but with an 12 layer PCB).

Extreme_Boky:



As Jaka & Guido said: This is impossible by Kirchhoffs law. The voltage between the two input pins of an OP is zero, with I = U * R there is no current running in the OP.

But if we discuss possible high frequency return path it might be better if you use an 4 layer PCB. A 6 layer (or more) PCB is not necessarily better than a 4 layer PCB.

the law is U = RI so I = U/R
if you have a wire with 0 ohms R, you can flow any amount of current into it, U = 0

so you can convert current to voltage with an impedance of 0R
 
apolon34 said:


the law is U = RI so I = U/R
if you have a wire with 0 ohms R, you can flow any amount of current into it, U = 0

so you can convert current to voltage with an impedance of 0R

Yes, and all information is gone - useful transformation

The discussion is about virtual grounds showing near zero input impeance. The traditional IV converter with opamp stil has resistance > 0 ohm.
 
once you have pwr and gnd internal planes I think you will find 2 routing layers adequate for any but the densest designs with lots of high pin count chips with unsolderably close (by hobbyist techniques) pin spacings - 4 layers really is good enough

if you are immune to the extra expense of 6 layers I would use layer 4 for misc (fat) pwr distribution partial planes - even digital today has multiple voltages
 
I have consulted companies in their design work, going from 6 layers with loads of problems to 2 layers passing all EMI tests.

Hi Guido,

your right, increasing the layer number not neccesarily reduces EMI problems or vice versa. Its important to do it the right way. And don't forget Maxwells laws...

An example is the placement of decoupling capacitors - the se should be as close a spossible to the ground pin of the IC being decoupled.

Well, I'd prefer saying: Minimize the area between capacitor and IC connections. As an interesting result you need not put your decoupling cap very close to the Vcc and GND pin of an IC. You can minimize the area by putting GND and supply layer of a multilayer als close as possible (about 100-200µm) and using power planes of course. The inductance of such a "stripline" (or should we say stripplane?) is VERY low. In this way a capacitor "far away" is efficient enough for IC decoupling. Some more advantages are: You need less caps and you need not place them close to the IC. I know this in a very unconventional way but it works up to frequencies of more than several GHz.

You can find more information here (click download and register):

http://www.emv.biz/service/index.php
 
Your DAC current flows through feedback resistor, output of opamp, opamp's power supply pin, opamp's power supply back to the ground of the power supply and ground connection between power supply ground and DAC ground connection, then again through DAC power pin, DAC's power supply and it's ground connection to the DAC's ground pin.

At least this is steady state. At transients, current also flows through parasitic capacitances, charging and discharging them.
That's exactly right. I think I am starting to understand how this works. It took me a while to understand that Vout pin is virtual ground.

There are two excellent very active threads available at the moment with a lot of info shared by everyone - very nice.

This is the other one:
http://www.diyaudio.com/forums/showthread.php?threadid=58727

Regards,
Extreme_Boky
 
Extreme_Boky said:

That's exactly right

"and ground connection between power supply ground and DAC ground connection, then again through DAC power pin, DAC's power supply and it's ground connection to the DAC's ground pin. "

:xeye: i still dont get that. DAC ground connection = DAC ground pin in my view. So i dont think that is exactly right.

Explain please
 
Ok,

The way I see it happening is this:
Current Iout from the DAC goes to the input pin of IC, through the feedback resistor to Vout pin. In my opinion this Vout pin is sitting at virtual DC ground through differential output transistor pair, + and - power supply rails, power supply - to analog ground.

Voltage drop generated across feedback resistor at input pin of IC gets amplified - this is our GAIN.

This whole story explains why the ground plane should be as large as posible. I have red also expert explanations in many articles that:” current will find a way..." without really trying to understand - let alone EXPLAIN what really goes on!!!

DAC ground pin shares the same analog ground plane...

Comments please....

Extreme_Boky
 
Hi,

let's see if I wrote this correctly. I assumed that hypotetical DAC and IV converter have separate bipolar power supplies. I then assumed that DAC is sourcing current out of output pin. IV opamp tries to hold DAC's output pin at ground potential (because that's where it's positive input is tied to), so it has to adjust it's output into negative direction until current through feedback resistor matches DAC's source current. So IV conversion actually works by balancing DAC's source current by IV's converter sinking current.

Since current flows in loops, that loop would be:

DAC's positive power supply source output pin - DAC positive power pin - DAC output pin - through feedback resistor - output of opamp - opamp negative supply pin - opamp's negative power source output pin - opamp's power supply ground connection - through connection between opamp's power supply and DAC's power supply - DAC's power supply ground connection.

So in this case DAC's ground pin is just sitting somewhere on the connection between both power supplies grounds doing nothing for the output current loop. The point is that there is current flowing through connection between opamp's power supply ground and DAC's power supply ground. If this connection is split into two parts with DAC ground pin in the middle as another node it changes nothing.

Hope things are a clearer now.

Best regards,

Jaka Racman
 
bocka said:


Hi Guido,

your right, increasing the layer number not neccesarily reduces EMI problems or vice versa. Its important to do it the right way. And don't forget Maxwells laws...



Well, I'd prefer saying: Minimize the area between capacitor and IC connections. As an interesting result you need not put your decoupling cap very close to the Vcc and GND pin of an IC. You can minimize the area by putting GND and supply layer of a multilayer als close as possible (about 100-200µm) and using power planes of course. The inductance of such a "stripline" (or should we say stripplane?) is VERY low. In this way a capacitor "far away" is efficient enough for IC decoupling. Some more advantages are: You need less caps and you need not place them close to the IC. I know this in a very unconventional way but it works up to frequencies of more than several GHz.

You can find more information here (click download and register):

http://www.emv.biz/service/index.php


Hi,

The loop area ofcourse should be made as small as possible. Nevertheless the decoupling should be as close as possible to the ground pin as to avoid common impedances in the ground plane.

The decoupled current (to the supply pin) will follow the internal current, if allowed. Therefor it is not neccessary to create a plane - a single trace is enough.

In addition, power planes may heavilly resonate with the ground plane as they form ultimate C networks - not my cup of tea.
 
Nevertheless the decoupling should be as close as possible to the ground pin as to avoid common impedances in the ground plane.

Yes that's what I do nearly every time. But powerplanes gives me the freedom of decoupling of the IC nearly anywhere on the PCB. I'll give it a try our next commercial processor plattform (with µBGAs and 266MHz busclock)

In addition, power planes may heavilly resonate with the ground plane as they form ultimate C networks - not my cup of tea.

Only if the characteristic impedance ist too high. With a characteristic impedance of 1 ohm or less powerplanes dampens any network resonance (with reasonable low inductance of the decoupling caps. i.e. not larger than 0402). Powerplanes act as transmission lines at highest frequencies.
 
bocka said:


Yes that's what I do nearly every time. But powerplanes gives me the freedom of decoupling of the IC nearly anywhere on the PCB. I'll give it a try our next commercial processor plattform (with µBGAs and 266MHz busclock)

Only if the characteristic impedance ist too high. With a characteristic impedance of 1 ohm or less powerplanes dampens any network resonance (with reasonable low inductance of the decoupling caps. i.e. not larger than 0402). Powerplanes act as transmission lines at highest frequencies.

The impedance the decoupling current sees is nearly independant of the width of the track because obviously the current won't neatly distribute across the plane. Have you ever measured the current distribution across such planes or tracks ? Amplitude as function of location ? Do it, it will increase insight in your theory.

Ofcourse processor PCBs are less critical than digital audio applications so go ahead and let the currents decide.

Damping only is provided by resistive elements - go back to your schoolbooks !
 
The impedance the decoupling current sees is nearly independant of the width of the track because obviously the current won't neatly distribute across the plane. Have you ever measured the current distribution across such planes or tracks ? Amplitude as function of location ? Do it, it will increase insight in your theory.

Transmission lines aren't lumped components. You cannot decouple frequencies above 10MHz or so (typical values: about 1nH parasitic inductance of a 0805 component and 100nF decoupling capacitor) with caps, because of its inductive component. I'm not talking about AF, I'm talking about decoupling in the 100MHz to several GHz range. Have you ever calculated/simulated the characteristic impedance of a powerplane? You'll see that the resisive component of copper (a lossy transmission line) will dampen oscillations with lowest characteristic impedance (as I've written before: less than 1 ohm!). Oh of course it depends of your substrate thickness, you will not see such effects with standard substates of 0.5mm. Schoolbooks sometimes worth to look in...

Ofcourse processor PCBs are less critical than digital audio applications

No, absolutely not! :whazzat: Have you ever build DDRRAM interfaces? Do it and you'll see that problems appear in audio applications are easy to handle. With datarates of more than 100MHz and harmonics above 1 GHz, cycle times in the ns and skew between clocks in the ps range a processor PCB is much more critical than audio.
 
Status
This old topic is closed. If you want to reopen this topic, contact a moderator using the "Report Post" button.