Hi again
J have found another schematic for 32 bit frame:
http://www.pedjarogic.com/1541a/I2Sbal_split.htm
J have done a pcb, but , J have just discovered that my cd pro deliver 48FS and not 64, is some one could explain me with a schematic how it is possible to split i2S from the cd pro. MY target is to have TDA 1543 balanced dac with the kit from DDDAC
J do not want to use CS 8412 and so on ...
Thanks a lot. j am a beginner and my knowledge is poor.
J have found another schematic for 32 bit frame:
http://www.pedjarogic.com/1541a/I2Sbal_split.htm
J have done a pcb, but , J have just discovered that my cd pro deliver 48FS and not 64, is some one could explain me with a schematic how it is possible to split i2S from the cd pro. MY target is to have TDA 1543 balanced dac with the kit from DDDAC
J do not want to use CS 8412 and so on ...
Thanks a lot. j am a beginner and my knowledge is poor.
gil-garcia said:
If you’re going the DDDAC route I see no justification for processing the +/- halves of each channel in the same DAC chip. It may matter when using a single pair of high-resolution chips, but the ‘1543 has very poor resolution and paralleling a number of them is intended to average out the non-linearity of the individual chips.
Attachments
Thanks for your help
j have noticed that it was possible just to invert data.
According to this thread and rfbrw, (http://www.diyaudio.com/forums/showthread.php?s=&threadid=20867&highlight=) the best solution seems to use glue logic with - and + on the same group of dac
j will try this way as j am waiting for à Kwak ASR
A link for 32 bit frame .
http://www.pedjarogic.com/1541a/I2Sbal_split.htm
j have noticed that it was possible just to invert data.
According to this thread and rfbrw, (http://www.diyaudio.com/forums/showthread.php?s=&threadid=20867&highlight=) the best solution seems to use glue logic with - and + on the same group of dac
j will try this way as j am waiting for à Kwak ASR
A link for 32 bit frame .
http://www.pedjarogic.com/1541a/I2Sbal_split.htm
gil-garcia said:
As I said, having the plus and minus of each channel on the same DAC may be preferable when using a single pair of quality DACs, but in your case, with dozens of TDA1543s, why bother. You should also realize that inverting the data introduces a DC offset in the differential output. The proper way is twos-complement negation but that requires a little more glue logic.
But, if you must…
Attachments
Thanks again
J have started the pcb, few questions
- this is the solution in order to have compatibility with the i2S from the cd pro ?
- j imagine that for bclK out j can take it directly from the input
- j do not know how to connect 74VHC164 each other :
j suppose that clk on your schématic is CP pin 8
For AB, it means j have to connect each other, the same for Q0....Q7
MR. what to do with it ...
Excuse me, my questions are for most of you basics but as j'am in marketing you can image my electronic education.
J have started the pcb, few questions
- this is the solution in order to have compatibility with the i2S from the cd pro ?
- j imagine that for bclK out j can take it directly from the input
- j do not know how to connect 74VHC164 each other :
j suppose that clk on your schématic is CP pin 8
For AB, it means j have to connect each other, the same for Q0....Q7
MR. what to do with it ...
Excuse me, my questions are for most of you basics but as j'am in marketing you can image my electronic education.
Attachments
Is this circuit what you need? I've got the schematic and PCB files in ExpressPCB format, but they are part of a larger circuit and it would take me some time to isolate them.
This is a working circuit--I've used it to route L or R audio to a TAS3004.
This is a working circuit--I've used it to route L or R audio to a TAS3004.
An externally hosted image should be here but it was not working when we last tested it.
Neil Davis said:
Interesting. It appears that when SW101 is in one position, the 64-bit sample frame contains two identical samples from one channel, e.g., mono left. When SW101 is in the other position, the 64-bit sample frame contains two samples from the other channel but taken from different sample periods. E.g., the right channel sample from the current sample period will be heard from one speaker at the same time the right sample from the previous sample period is heard from the other speaker. Also, the 74AHC594 will delay the transition of the data bits by ½ clock period: I hope that delay is accommodated elsewhere in the circuit.
whatsup said:
Right--
I needed this circuit because the TAS3004 input doesn't have the switching flexibility of the more recent digital audio processors. The TAS3004 is being used as a crossover so I needed to have the same data on the TAS3004 L/R inputs so one channel could be used for the woofer and the other for the tweeter. The switch determines whether the amp is used in a right speaker or a left speaker.
This circuit isn't exactly what was asked for, but I thought someone might find it useful. I've got a simple timinig diagram for it in Visio and two different PCB layouts (one even has an STA120 SPDIF circuit).
Neil Davis said:
Wrong-- I understand what you intended the circuit to do and you may have been happy with the results. I was just pointing out two subtle errors that you, and probably others, would miss.
The data that passes through the shift registers is delayed 1/2 clock cycle compared the data that goes directly to the mux. Such a skew in data transition timing is not kind to the DACs or other circuits that follow because it violates the setup and hold requirements and that leads to data errors.
As I pointed out, one of the channels combines the data from the current sample period with data from the previous period. Perhaps you don’t understand how that can happen or you don’t care because it sounds OK to you. Either way, I don’t think your schematic is a good example for anyone else to copy.
whatsup said:
I didn't have a choice on the 32-clock delay because the TAS3004 internally is expecting L/R and I wanted either L/L or R/R. There's no other way to "trick" the TAS3004 and for my application it results in a 7ms delay between the woofer and tweeter. That's not an error or an oversight--that's just a penalty for using the TAS3004, but one that can easily be compensated for (it is usually desirable to delay the tweeter, anyway, for a flat baffle).
I don't understand your comment about being off by 1/2 clock. The I2S data is clocked out on the falling edge of Fs clock. U106 inverts Fs clock so that data is clocked out of the '594 at the same time (RCLK--pin 12--uses a rising transition to clock the data out) . The '594 samples the data on the rising edge of Fs using SCLK, which is correct. What is "wrong" here?
Neil Davis said:
Code:
FRAME 1 FRAME 2 FRAME 3 FRAME 4
U105 pin 1 LLLLHHHH LLLLHHHH LLLLHHHH LLLLHHHH
U105 pin 2&6 L1..R1.. L2..R2.. L3..R3.. L4..R4..
U105 pin 3&5 ??..L1.. R1..L2.. R2..L3.. R3..L4..
U105 pin 4 ??..R1.. R1..R2.. R2..R3.. R3..R4..
U105 pin 7 L1..L1.. L2..L2.. L3..L3.. L4..L4..Each frame output from U105 pin 4 contains right channel data from two different sample periods.
Neil Davis said:
Upon further review I withdraw my comment regarding the ½ clock delay. Your use of the ‘594 is unconventional and I didn’t think it through. The usual way is to use a ‘164 clocked with BCLK, the same as the DAC. Provided the propagation delay through the ‘164 and following logic, if any, exceeds the data hold time of the DAC, the ‘164 can be thought of as an extension of the shift register inside the DAC chip. Compared to the ‘594, the ‘164 has fewer pins, fewer clocks, fewer internal gates, giving a simpler circuit with less ground bounce and noise.
An externally hosted image should be here but it was not working when we last tested it.
J haven't already done the split for the cd pro, but j can say that the schematic from pedja is working very well. j 'am using it with a CS8414 + reclocking + XO, 74HC161 for dem clock, ....
HEF4517 is from philips.
At the outpout, there is a dil in order to add a 74HC125N
Each circuit has it 's on régulation with TL431.
For the clock : jung regulator.
On each channel j have 12TDA 1543 in // with rikken and 20uf pio.
It works in symetric mode with the UGS.
j have to finished my 2X 2tda1541 in // with D1.
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