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Old 13th May 2005, 04:19 PM   #1
burbeck is offline burbeck  United Kingdom
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Default spdif input circuit help

hi
has anyone got a circuit 75 R spdif consumer to ttl levels, i have been using this one but having problems with oscillation (elekor design i think) tried using different versions of the ic.
regards
bob
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Old 13th May 2005, 05:40 PM   #2
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http://www.epanorama.net/documents/audio/spdif.html

Check there..

Bye,
Paolo
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Old 13th May 2005, 07:19 PM   #3
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Reduce R18 to 1 K. Reducing it past that probably won't help much. Get rid of C12. Make sure that it is the HCU04 version.

Some guys say that it has a tendency to oscillate with no input......I never had problems. Bypass, bypass, bypass. Keeps leads short.......etc.

Jocko
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Old 13th May 2005, 09:22 PM   #4
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Hi !

1st make sure that it is 74hc_U_04
The U stands for unbuffered. each inverter is just a komplimentary fet-pair. with R2 X5 is driven to his working point (yes it's analog !)
2nd the circuit should work fine :-)

i use the same circuit without R18 and without C12.
Some people vary R18 between 0 - 10K, some people use a 10k resistor from output X5 to ground ...

telefunken use in his DA1000 a transformer with a transistor after instead.

There are many ways :-)


Regards

Jobstens
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Old 13th May 2005, 09:38 PM   #5
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Leave R18 in. The open-loop gain of an inverter is usually around 20 or so. Some may be a bit higher, but 50 is definitely the upper limit. Lowering it after a certain point buys nothing. Except:

Taking it out will lower the input Z. While 1K in parallel with 75R won't throw it off too much, 2K will lower it less.

Jocko
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Old 13th May 2005, 11:11 PM   #6
burbeck is offline burbeck  United Kingdom
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thanks guys, i have played around with this circuit as described no joy. i was hoping that someone would offer a totaly new design
bob
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Old 14th May 2005, 12:07 PM   #7
gmarsh is offline gmarsh  Canada
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I've built this and it's stable...

New SPDIF input circuit.

Warning though, it doesn't get full Jocko approval.

I have no idea how much jitter the circuit adds - I'm thinking/hoping that hysteresis-induced phase noise is up in the MHz region, which a CS841x loop filter can eliminate and an AD189x ASRC can completely destroy. One of these days I'll feed the output of it back into the AP System Two and measure it.
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Old 14th May 2005, 02:24 PM   #8
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Hi Gmarsh,

I built Elso's spdif input circuit with the ad8561 and it seems to work well. Have you compared yours to his circuit and how is it different/better?

Thanks,
300_baud
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Old 14th May 2005, 03:31 PM   #9
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I don't know why you had trouble with it. An 'U04 inverter is only a pair of CMOSFETs tied together. It doesn't get much simpler. Did you use the right one...........i.e., unbuffered?

I have other circuits, but probably more than a noob wants to futz with.

Yes, Elso's circuit does work. But the diodes start to conduct, and that throws off the actual impedance that the signal sees.

We won't discuss hysteresis. Been done before. Although we would like to see if someone can measure its effect.

Jocko
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Old 14th May 2005, 04:32 PM   #10
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hi Jocko,

Can you post some spdif input schematics that you would recommend even if they are more difficult to assemble? I wouldn't mind trying them out.

Thank,
300_baud
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