Strange Teac DAC

[Bernhard]

Hi,

again, what happens here in my 1 x PCM53 for both channels TEAC ZD700 ?
Still I do not understand the circuit except that left and right must be separated.

Is this non-os ?
In pic 1 the sine consists of 44 spikes, and
in pic 3 there are 44 stripes on the bargraph inside a 1kHz sine = 44 kHz ?
Sine is 0 dB.
The bargraph remains when player is on pause.
Is the bargraph some kind of help-signal ?

Schematic + scope pics:

[apolon34]

that seems like decimation.

here's a link that explain it:
http://www.tnt-audio.com/clinica/convertusdecima_e.html

[Bernhard]

Thanks,

looks really like decimation and maybe they applied also dither,
the bargraph is noisy and when I look at the schematic now spontanously I see the following possibility:

the switch close to 6 removes the audio samples from the signal, leaving the noise and the inverted noise is added to the original signal so that the noise cancels at the resistor bridge at 7.
I made mistake reading the values it is 15k, not 150k. Very small resistors...

Now is that decimation done in the analog or digital domain ?

The low level performance of that DAC is the best of all multibits I have seen and I want to built it with two DAC chips but now it becomes tricky...

Is there a way to use the left deglitch and right deglitch signals to separate the left/right data for two DAC chips ?

Comments ?

[guytou]

Hi bernard , isn't your sheme a simple sample and hold for early 1DAC/CDP's ? It could'nt be decimation here because decimation operates in the digital domain , no ? Wich DF is before the DAC ?
I am looking too for a sheme that could recover L/R data from data flow , advises welcomed .

[rfbrw]

Originally posted by guytou
Hi bernard , isn't your sheme a simple sample and hold for early 1DAC/CDP's ? It could'nt be decimation here because decimation operates in the digital domain , no ? Wich DF is before the DAC ?
I am looking too for a sheme that could recover L/R data from data flow , advises welcomed .

From what dataflow?

[Bernhard]

Originally posted by guytou
isn't your sheme a simple sample and hold for early 1DAC/CDP's ? It could'nt be decimation here because decimation operates in the digital domain , no ? Wich DF is before the DAC ?

Usually S/H is only 2 x S/H for early 1DAC/CDP's like indicated as functional unit around 1 in the schematic.
All those circuitry that I have drawn detailed in the schematic, I have never seen in any datasheet of old DAC chips like PCM53, 54, 56...

Maybe it is not decimation , when I make the S/H cap very small around 220pF, it looks like 1 before the filter also in my 4 x os PCM53 DAC that I built for testing.

When adjusting the pots there is pink noise that can be adjusted to disappear, so there must be something like dither.

The OS chip is TEAC 52200492-00

[Bernhard]

Originally posted by rfbrw



From what dataflow?

rfbrw,

you are one of the great Manitou here ,
don`t you have an idea about this circuit ?

Is it possible to feed the parallel 16bit data from that TEAC chip to a pair of latches and update the contents of the latches with the two deglitch signals ?

Or split the left/right data before the TEAC chip and use two chips.

Denon DCD1500 also uses a pair of mono os filters SM5801, but PCM53 is not good with them.

[guytou]

Hi rfbrw , the serial/parallel dataflow,if i am right , i.e. the one that comes from YM3613/CXD2500 decoder .

[moamps]

from old Tascam CD501 SM:

[moamps]

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