Word Clock Distributor design

[matrixtwelve]

Hello List:

I am building a Word Clock Distribution box to distribute WC from my RME ADI-88-DD (which has only one WC output) to 11 devices in my studio. If I understand correctly I can route the WC (from a BNC "WC input" connector on my diy chassis) directly to the inputs of 10 HC family gates which will buffer the clock input. Then I connect the outputs of these gates to BNC connectors, with a 75 ohm resistor to ground on each output. Is this correct?

Has anyone posted any schematics of how to do this properly? I searched the archives but could not find any relevant material.

Thanks for any input,

Keith

[OliverD]

I suspect you would need to connect the 75 Ohms resistor between the gate's output and the "hot" pin of the BNC connector at the TX end, and from BNC "hot" pin to ground (as you described) at the RX end.

But better wait for some comments from our digital interface experts...

[rfbrw]

Originally posted by OliverD
I suspect you would need to connect the 75 Ohms resistor between the gate's output and the "hot" pin of the BNC connector at the TX end, and from BNC "hot" pin to ground (as you described) at the RX end.

But better wait for some comments from our digital interface experts...

http://www.diyaudio.com/forums/showthread.php?postid=275730#post275730

Post 115 has the schematic of a simple clock distribution scheme. Note the series resistors.

[Ulas]

Or, you could use a proper clock driver. Take a look at the 49FCT2805. It has a 1:11 fanout and has integrated series resistors. Closely related is the 'FCT807. It is only 1:10 fanout so you will need two of them and supply your own series rersistors. I designed a small PCB that holds two '807s and resistors and plugs into a normal 24-pin DIP socket. It makes a handy 2x10 clock distribution "chip."

[Jocko Homo]

That is one way, but..........

How long are these cables going to be? I suspect that they would be too long for that simple scheme, which was intended for a few cm at most. WC is 64 x Fs?

First, in order for your idea to be right, you would need to reduce the buildout resistor so that the impedance is 75R. If you are using HC logic, figure around 25 ohms less. (I would of course measure it, as each brand is a bit different.)

But 10 gates............2 packages at a minimum......all operating in unison will add jitter. Picogate time.

Or................maybe better.........for long runs and higher frequnecies.......use video buffers. Terminate the far end in 75R. Would entail using a 2X op-amp to bring it back up to logic levels.

Jocko

[Ulas]

Originally posted by Jocko Homo
WC is 64 x Fs?

WC = Fs.

Picogates don't address the fanout problem nor do they address clock skew. Each picogate will likely have a different prop delay.

What's the difference between 1 package with 10 gates all switching simultaneously or 10 packages with 1 gate each all switching simultaneously?

[Jocko Homo]

Right, I am thinking bit clock. Never had a need to send 44 kHz everywhere.

Each package would have its own Vcc and ground connection, and you would isolate the Vcc pins with ferrites. Less di/dt per connection.

At 44 kHz.......one driver may work. It would depend on length.

Jocko

[dhaen]

Consider using the Elantec EL2099 - now available form Intersil:
datasheet
It can supply 6* 75ohm terminated lines.
Wordclock distribution is much the same task as video distribution except for the larger signal swing. This is easily accomodated with this chip.
Be careful to keep the feedback path short and avoid parasitic capacitance around the invering input pin.

I see you'll need 2!

[Ulas]

Originally posted by Jocko Homo
Each package would have its own Vcc and ground connection, and you would isolate the Vcc pins with ferrites. Less di/dt per connection.

In case you don't get around to looking at the '807 datasheet, it has four VCC and five GND pins per package which allow ample opportunity for bypassing and isolation. With multiple gates within a single package the operational characteristics of each gate are more closely matched. Unlike ordinary logic, clock drivers are specified more tightly and are speed graded. You rant about the prop delay differential between Q and Q-bar in the same flip flop: What do you think the prop delay differential between two picogates is? I’ve never seen a picogate, one-gate, or tiny-logic datasheet that specified package-to-package output skew. Have you?

[Charles Hansen]

Originally posted by Ulas
What do you think the prop delay differential between two picogates is?

You are correct about this point. However, if you read the initial poster's question, this parameter has no bearing in his application.