Elegant way to feed parallel data-input DAC chips ?

[Bernhard]

Originally posted by bitrate


Of course You will need software like Xilinx WebPack or Altera Quartus2

Is this or other similar stuff available in DIP package ?

Does it need a hardware programmer ?

I have never played with any PIC , gate array , Pal or Gal or whatever

What is best to substitute lots of cmos logic like counters, flipflop, gates... ?

Easy programming, low chip and programming-hardware cost ?

[bitrate]

Most CPLD's are ISP (in system programmable via JTAG interface) and SMD devices (all?) but some packages are user friendly

[rfbrw]

Originally posted by Bernhard


What hardware do I need to do that ?

1. Some free software available from the likes of

www.altera.com
www.latticesemi.com
www.xilinx.com

All software options above allow schematic entry and unless you plan to move on to FPGA's, DSP and the like, I would not bother clouding the issue with whether to opt for VHDL or Verilog. Unless you are competent in hardware design using a HDL would just be a distraction

2. A download cable needed to program the CPLD in situ.
You can buy or make one.

3. A suitable device. As a beginner I'd steer clear of exotica like MAX2, Coolrunner2, XPLA3, ispXPLD etc. They either come in very user unfriendly packages or run off 1.8/2.5/3.3 volts or both.
Go with something like the 5v XC9500 or the 5v MAX7000.
In this case, given the number of pins required I'd go for gmarsh's XC9572 in 84pin PLCC package. Sorry no DIP, dude.

[bitrate]

If You want replace logic circuit with lots of gates like TTL's CPLD is great solution and relatively cheap if to take under attention PCB board space savings and its proper design , power management system , noise added by logic to other electronics components on the board .You can reprogramming it like classic EEPROM/Flash device ( 10000program/erase cycles- 10 years program retention)It also allow to logic level conversion (one power suplly for core ,other for i/o)

[bitrate]

This are results from simulation my simple serial/parallel converter for AD5547 DAC ( this is not an audio DAC )

Regards

[bitrate]

and its improvements:

added latch at output data [0..15]

[Bernhard]

Originally posted by bitrate
This are results from simulation my simple serial/parallel converter for AD5547 DAC ( this is not an audio DAC )

If I will ever have the time, I will try programming chips, for now the Denon chip will do, hopefully.

DAC71 nicely fits the PCM53 socket but got visible nonharmonics.

[bitrate]

Of course it is early iteration of this converter ,look at signal ldac it is inappropriate ,it should be one bck pulse for load internal latch data to output , and for proper load to internal latches it should stay low for remaining time to next load ,I fixed it recently .So You will also need simulator ,and some knowdlege how to write testing stimults or good and easy to use waveform maker like online Timing Tool
Regards