I'm designing the attached circuit into something i'm building. I don't like using 74HCU04 gates for signal recovery - in a few cases, I've had them oscillate when no input is connected.
This circuit has hysteresis which should prevent any of that from happening. At MHz frequencies, the input impedance should be 82.5 || 1820 || 1820 || 7500 = 74.887 ohms, which is easily within the impedance tolerance of the connecting cable and since i'm building the thing with 1% resistors anyway, I think i'm OK there.
I've only guessed at the 10K hysteresis resistor. Since the input is biased to ~0.65 volts and the output swings from 0V to around 2.8V, the hysteresis isn't symmetric - the 7500/1820 pair on the reference will probably change slightly to balance this out. I'm thinking +-25mV would be a good hysteresis window.
The AD8611 is probably overkill, but I can't find any other fast high speed comparators that are happy at 3.3V.
Thoughts?
This circuit has hysteresis which should prevent any of that from happening. At MHz frequencies, the input impedance should be 82.5 || 1820 || 1820 || 7500 = 74.887 ohms, which is easily within the impedance tolerance of the connecting cable and since i'm building the thing with 1% resistors anyway, I think i'm OK there.
I've only guessed at the 10K hysteresis resistor. Since the input is biased to ~0.65 volts and the output swings from 0V to around 2.8V, the hysteresis isn't symmetric - the 7500/1820 pair on the reference will probably change slightly to balance this out. I'm thinking +-25mV would be a good hysteresis window.
The AD8611 is probably overkill, but I can't find any other fast high speed comparators that are happy at 3.3V.
Thoughts?
Attachments
Yes, oscillation is bad, but........................
Hysteresis works by regenerative action: energy is coupled back to the input. Becomes the equivalent of an impedance glitch.
Think linear. Phred likes video op-amps. Enough hints for someone as smart as you.
Send me an e-mail when I get back to the office, about 1 week.
Jocko
Hysteresis works by regenerative action: energy is coupled back to the input. Becomes the equivalent of an impedance glitch.
Think linear. Phred likes video op-amps. Enough hints for someone as smart as you.
Send me an e-mail when I get back to the office, about 1 week.
Jocko
I'm confused.
Thing is, i'm not directly applying any sort of current back to the input - i'm shifting the reference voltage to which the input is compared. The input sees the - terminal, nothing else.
Of course, having the + terminal move by 10mV or so might cause a slight preturbance on the - terminal, perhaps by slightly changing the - bias current, or due to stray capacitance between + and - terminals... I can't find any literature or anything on things like that.
hmm...
<goes hunting for video amps>
Thing is, i'm not directly applying any sort of current back to the input - i'm shifting the reference voltage to which the input is compared. The input sees the - terminal, nothing else.
Of course, having the + terminal move by 10mV or so might cause a slight preturbance on the - terminal, perhaps by slightly changing the - bias current, or due to stray capacitance between + and - terminals... I can't find any literature or anything on things like that.
hmm...
<goes hunting for video amps>
Hi,gmarsh said:
Why 3.3V?
I am using the same 5V as the CS8412. AD8611 is a bad chip I feel. What you need is a balanced direct drive to the DIR. Ask Jocko why.
http://www.diyaudio.com/forums/showthread.php?postid=29208#post29208
See also further on in this thread for a improved circuit.
Hi !
I wonder about PECL comparators such how : ADCMP561 as an input receiver .At their outputs is avilable fully balanced digital signal ,and PECL logc is well known from possession of small crosstalks ,EMI disturbance ,it also has very good timing characteristics .The logic level converter from PECL to CMOS LVCMOS may be necessary .What do you think about this?
I wonder about PECL comparators such how : ADCMP561 as an input receiver .At their outputs is avilable fully balanced digital signal ,and PECL logc is well known from possession of small crosstalks ,EMI disturbance ,it also has very good timing characteristics .The logic level converter from PECL to CMOS LVCMOS may be necessary .What do you think about this?
Re: Re: New SPDIF input circuit.
I'm using 3.3V because everything digital in this project (CS8416, SRC4192, XC9572XL, ATMega8L, etc) runs off 3.3 volts. Using a 5V comparator (LT1016/TL3016/etc) would involve doing a 5V->3.3V logic conversion and adding an extra regulator and capacitance for a digital 5V rail. Adding -5V would be annoying.
The "improved circuit" still has one flaw in my mind - with the input disconnected, both + and - on the comparator are zero. IMO, the circuit should be in a known and/or fixed state with no input... either by hysteresis or by a voltage offset. I can't rely on the offset voltage of the comparator to keep things stable...
I also have a Toslink input on this project, so doing a balanced drive isn't really suitable. I suppose I could do a 2:1 MUX using CMOS and then use an XOR gate for balanced drive into the '8416...
And yes, you would need a PECL->TTL converter like a MC100ELT21 - which also happens to work well on its own as a comparator, with a limited voltage input range.
Why do you feel the AD8611 is a bad chip?Elso Kwak said:Hi,
Why 3.3V?
I am using the same 5V as the CS8412. AD8611 is a bad chip I feel. What you need is a balanced direct drive to the DIR. Ask Jocko why.
http://www.diyaudio.com/forums/showthread.php?postid=29208#post29208
See also further on in this thread for a improved circuit.
I'm using 3.3V because everything digital in this project (CS8416, SRC4192, XC9572XL, ATMega8L, etc) runs off 3.3 volts. Using a 5V comparator (LT1016/TL3016/etc) would involve doing a 5V->3.3V logic conversion and adding an extra regulator and capacitance for a digital 5V rail. Adding -5V would be annoying.
The "improved circuit" still has one flaw in my mind - with the input disconnected, both + and - on the comparator are zero. IMO, the circuit should be in a known and/or fixed state with no input... either by hysteresis or by a voltage offset. I can't rely on the offset voltage of the comparator to keep things stable...
I also have a Toslink input on this project, so doing a balanced drive isn't really suitable. I suppose I could do a 2:1 MUX using CMOS and then use an XOR gate for balanced drive into the '8416...
The ADCMP561 seems like overkill for the application... a 1ns comparator is nice for something like a superfast logic analyzer with a several-hundred-MHz bandwidth, rather than a SPDIF decoder.bitrate said:
And yes, you would need a PECL->TTL converter like a MC100ELT21 - which also happens to work well on its own as a comparator, with a limited voltage input range.
Re: Re: Re: New SPDIF input circuit.
Hi, The AD8611 does not sound good in my clock, jitter?
The AD8561 can operate on a 3.3V single supply. The 5V->3.3V logic conversion is hardly necessary as the AD8561 outputs typically 3.5V as a logic high and most 3.3V logic is 5V tolerant on the inputs.
I never had a stability problem with the comparator at the input. I am sure Maxim has some nice comparator capable of operating on 3.3V.
The balanced drive was just a hint.....
gmarsh said:
Hi, The AD8611 does not sound good in my clock, jitter?
The AD8561 can operate on a 3.3V single supply. The 5V->3.3V logic conversion is hardly necessary as the AD8561 outputs typically 3.5V as a logic high and most 3.3V logic is 5V tolerant on the inputs.
I never had a stability problem with the comparator at the input. I am sure Maxim has some nice comparator capable of operating on 3.3V.
The balanced drive was just a hint.....
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