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Old 22nd March 2005, 05:46 PM   #1
Bricolo is offline Bricolo  France
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Default Jitter, Clock Distribution and Glue Logic

Hi all,


I'm thinking about clock distribution schemes; for a cd player mod. I know there are many possibilities, but I often read things here about using mutiple gates in one package/using both outputs of a gate/loading a gate with more than one input... relative to jitter.

I need a clock, feeding the decoder chip, the digital filter, and the dac (maybe divided by 4 if I go for non os). So 3 outputs, plus some if I want to try reclocking, or DEM reclocking on the 1541.

What bould be the right way to do this? Using the clock's output (certainly a Kwak Clock) to feed directly 4 chips? Connecting a buffer, then the 4 chips, 4 buffers... something else?


And I'd like to understand what causes the jitter in these chip outputs, if we use Q and Qbar simultanously, if we put too much glue logic on a gate's output. Since I need more than one output, at least one output will have 4 things on its output, even if it is "only" buffers. And if I need an inverted output, use the Qbar on the Kwak Clock's comparator, or add an inverter (why?)?


So many unansweared questions...

Thanks
Alex
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Old 22nd March 2005, 07:54 PM   #2
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Bricolo,

don't mix up the Q / Qbar rants of Jocko with the clock distribution problem.
Jocko seems to be against the use of D flipflop Q / Qbar outputs when generating a balanced drive for SPDIF. For example, if you want to drive a transformer like T4-6T, take the CT side, put CT on ground, and drive the coils from Q and Qbar [accross a cap].
In this way the power supply glithces, which appear at the bit switching time at the '74 PS, would be presented like common mode to the transformer, and be supressed. And this is good.
Moreover, in this way the Dflop's output current is constant, and this helps to decrease the PS changing, which would cause time shifts.

But Jocko's point here, as far as I understood, is that the prop. delay time from CKin to Q, and from CKin to Qbar, are different.
Given the fact that the data sheets are mute about it [they declear the same value for both, and even emphasize that they [the prop delays] are "balanced", I got curious, and settled down to measure it.
Again, this is not a very easy measurement, because at first glance it seems to be like the datasheet says - the prop delay is the same.
For example, in case of a clock signal of 10 MHz, and Qbar fed back to D, [so you have 100 nSec between changing edges], in case of an HC74, the delay is ~18 nsec, and the edge rise/fall times are 5-6 nsec.
Now, if you go to 500 psec /div, this 6nsec rise time becomes a slooow slope.. and there you should look for very small differences.
But it seems to be that Jocko is right. In case of the HC, I saw ~160pSec time shift between the Q and Qbar outputs.
In case of an F74, prop. delay time is less, ~ 6-7 nsec, the rise/fall times are more neat, but still, or again, there is a difference of ~ 140pSec. [interestingly, it changes polarity, though]

Though ~150 pSec time difference is really very small in absolut terms, when someone wants to arrive at several picosecs jitter values, it suddenly becomes huge..

I think this is what Jocko intended to say. [Would be nice to have a confirmation..]

But, when you want to distribute the clock, you anyway will have delay times introduced by the line lenght [~ 500 pSec /10cm ], so these 150 pSecs become meaningless. Anyway, no matter how many clocks are distributed, there will always be only one really important, which will do the effective, final reclocking before entering the dac. I would take the original clock output directly there. [and very close] Then, maybe take the Qbar output, and buffer it as you want, invert it again if needed, the jitter introduced does not [should not ] matter anyway! What you should care about is the setup/ hold time requirements only.
The DEM reclocking is a good question, it would be nice to know a bit more about it, how much perfectly should you be synchronized..
It will be a tough task, to do it right, anyway..

Ciao, George
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Old 23rd March 2005, 03:11 AM   #3
gmarsh is offline gmarsh  Canada
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On flip flops... In one case, I drove a 49.152MHz clock into a 74HC74 chip, which was configured to divide the output by four. I didn't have VHC parts available at the time, so I ran the HC part out of spec and hoped that it'd work... well, it didn't.

Q on the first divider put out 49.152 divided by two.
/Q on the first divider out 49.152 divided by THREE.

Looking at /Q on the scope, it was high for two input clock cycles, and low for one. Obviously there's more than just a single inverter inside these chips to provide /Q...

If memory serves me right, the 74HC74 was a ST part.
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Old 23rd March 2005, 08:09 AM   #4
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Default Re: Jitter, Clock Distribution and Glue Logic

Quote:
Originally posted by Bricolo
Hi all,


I'm thinking about clock distribution schemes; for a cd player mod. I know there are many possibilities, but I often read things here about using mutiple gates in one package/using both outputs of a gate/loading a gate with more than one input... relative to jitter.

I need a clock, feeding the decoder chip, the digital filter, and the dac (maybe divided by 4 if I go for non os). So 3 outputs, plus some if I want to try reclocking, or DEM reclocking on the 1541.

What bould be the right way to do this? Using the clock's output (certainly a Kwak Clock) to feed directly 4 chips? Connecting a buffer, then the 4 chips, 4 buffers... something else?


And I'd like to understand what causes the jitter in these chip outputs, if we use Q and Qbar simultanously, if we put too much glue logic on a gate's output. Since I need more than one output, at least one output will have 4 things on its output, even if it is "only" buffers. And if I need an inverted output, use the Qbar on the Kwak Clock's comparator, or add an inverter (why?)?


So many unansweared questions...

Thanks
Alex
Hi

Good and interesting thread. The balancing act requires analogue solutions, ore clever use of ff's. You could imagine using 2 Q outputs and drive the inputs differentially, but then again, the problem is shifted backwards

On the clocking scheme:

I'd suggest to put the oscillator as close as possible to the DAC chips (close means close).

Drive the DAC chips directly from the clock output, and then use a single (picogate) inverter/buffer to drive the other chips.

Needless to say one should pay attention to layout and decoupling issues.

Ciao
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Old 23rd March 2005, 08:51 AM   #5
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Default Re: Jitter, Clock Distribution and Glue Logic

Quote:
Originally posted by Bricolo
Hi all,


I'm thinking about clock distribution schemes; for a cd player mod. I know there are many possibilities, but I often read things here about using mutiple gates in one package/using both outputs of a gate/loading a gate with more than one input... relative to jitter.

I need a clock, feeding the decoder chip, the digital filter, and the dac (maybe divided by 4 if I go for non os). So 3 outputs, plus some if I want to try reclocking, or DEM reclocking on the 1541.

What bould be the right way to do this? Using the clock's output (certainly a Kwak Clock) to feed directly 4 chips? Connecting a buffer, then the 4 chips, 4 buffers... something else?


And I'd like to understand what causes the jitter in these chip outputs, if we use Q and Qbar simultanously, if we put too much glue logic on a gate's output. Since I need more than one output, at least one output will have 4 things on its output, even if it is "only" buffers. And if I need an inverted output, use the Qbar on the Kwak Clock's comparator, or add an inverter (why?)?


So many unansweared questions...

Thanks
Alex

Hi Bricolo, The AD8561 used in my clock can drive 20 TTL logic gates so I won't worry too much and connect the ouput directly to the chips needing a clock with a short connection as possible. If you need an inverted ouput you can use the second inverted output of the AD8561. Rbroer has used that to advantage.
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Old 23rd March 2005, 09:50 AM   #6
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Guido!

Quote:
You could imagine using 2 Q outputs and drive the inputs differentially, but then again, the problem is shifted backwards
As Jocko suggested, a HC86, driven by the flop Q, wired out of phase.

Ciao, George
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Old 23rd March 2005, 12:22 PM   #7
Bricolo is offline Bricolo  France
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Hi


-George
So, the problem isn't "loading Q abd Q/ at the same time" but comes from the different propagation delays? Is the delay between Q and Q/ different on all gates? (All brands, all types)


-gmarsh
Interesting. What's the max frequency for HC logic? 40MHz? Maybe the FF was loaded just a little too fast, this combined with different rise time and fall time, could lead to such beaviour.


-Guido
Thanks
Using an inverter and 2 FF still had this timing problem, but the inverter may add less delay than the delay difference between Q and Q/
A possibility would to use 2 FF, and 2 XOR gates. One XOR having the clock and 0, the other would have the clock and 1. So the 2 lines have the same number of gates, and exactly the same gates. The delay should be null.
But all of this mean more glue logic, and I don't remember who told this on this forum, but "more logic gates means more jitter"

About the clock distribution: by using the "clean clock" as BCK for the DAC (instead of the BCK output from the decoder/filter) the new clock's edges aren't certainly synchronized to the other I2S lines's edges (normally, all I2S lines including BCK are coming from the same decoder/filter chip, so the edges occurs at the same time). Isn't this jitter too?


-Elso
I agree with you, the comparator is able to drive many gates (you're certainly referring to the fan out/fan in). But I've read many times that loading an output with many gate inputs leads to jitter, that's one of the reasons for this thread.


And if I need a 2.8MHz clock (for a NON OS DAC), how should I make it? Dividing by 4 most obviously, but how? An IC counter (what kind of?) 2 DFF?



Thanks
Alex
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Old 23rd March 2005, 12:49 PM   #8
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Bricolo,

Quote:
Using an inverter and 2 FF still had this timing problem, but the inverter may add less delay than the delay difference between Q and Q/
A possibility would to use 2 FF, and 2 XOR gates. One XOR having the clock and 0, the other would have the clock and 1. So the 2 lines have the same number of gates, and exactly the same gates. The delay should be null.
The answer is in my post above. If you take the D flop's Q output, and buffer it with a couple of XOR [HC86] inverting & non, and then take this through the due resistor divider network + cap decoupling to the balanced transformer coils, then a nice little zobel on output, and all this directly onto the pins of a 75 ohm BNC, then you have done a good job.. [jocko?]
This way all the benefits of the balanced operation remain valid, with no time shift between inverted & non, and the D flop, although now works single - ended, now only drives the XOR gate inputs, which are a light load, will not cause power supply ripple [too much]. Maybe a damping resistor between Dflop & XOR input.
A problem remains - will be the balanced transformer leakage inductance much worse, than that of a good [Schott?] 1 : 1 transformer? [Probably yes] Can it be corrected for by the Zobel?
The advantage gained in the balanced operation will be lost in the not appropriate transformer usage?
You see, also I have some questions.. [maybe I will play with it]

Quote:
So, the problem isn't "loading Q abd Q/ at the same time" but comes from the different propagation delays? Is the delay between Q and Q/ different on all gates? (All brands, all types)
a./ Yes. b./ types different yes, brands I don't know

Ciao, George
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Old 23rd March 2005, 12:59 PM   #9
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Gmarsh,

Nice story!

For your attention, if you hadn't known:
"getting more speed from a logic family"

ciao, george
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Old 23rd March 2005, 05:02 PM   #10
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Hi,

I also have a problem, tried to stack BB DAC chips and the NPC os filter was not able to drive more than 3 chips per channel.
What is the best way to buffer the signal for distrbution in this case ?
A comparator ?
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