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Old 7th September 2010, 08:33 AM   #14921
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Ooo that's a good price

I'll have one please!

Brent
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Old 8th September 2010, 07:28 PM   #14922
6h5c is offline 6h5c  Netherlands
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Quote:
Originally Posted by RCruz View Post
"In the buffer I have added a current sink, replacing the 1.8k resistor. This is an addition of another 2SK170BL and a couple of resistors."

I do not see this current sink in Ray´s schematic.... can you please elucidate ?

I do not believe this board can fit inside my CDP.... can I mod the existing DOS ?
Hi Ricardo,

The DOS-CFP page is still under construction, and the schematic only shows the added transistors in the input stage, which is the essence of the CFP version.

The 1k8 resistor may be replaced by a current source. It was added later and can be applied to the original DOS circuit as well. I hope to update it soon with some text on Steve's new board and I will put up a specific schematic of it.

Regards,

Ray
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Old 8th September 2010, 08:13 PM   #14923
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Thank you so much Ray

I will wait until you get everything sorted out.

What should be the advantages of such CCS ?

Ricardo
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Old 9th September 2010, 03:28 AM   #14924
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Quote:
Originally Posted by RCruz View Post
Thank you so much Ray

I will wait until you get everything sorted out.

What should be the advantages of such CCS ?

Ricardo
FWIW,
I added the current sink to my board before I ever heard of the CFP. It didn't make any difference. The CFP makes a difference.

Steve
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Old 9th September 2010, 03:44 PM   #14925
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The input stage and output transistor are directly coupled, so any variation of the input stage current will have an effect on the operation point of the output transistor. The current source makes the operating point of the output transistor independent of the input stage. It will set the current to 10mA, whatever the input stage does.

I want to draw a new schematic anyway, so when do, i'll do some simulations with and without CCS, to see if there's less distortion.

Ray
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Old 9th September 2010, 07:54 PM   #14926
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Thank you Ray.
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Old 11th September 2010, 02:49 PM   #14927
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Okay, here's a schematic as requested.

Current Sink.gif
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Old 11th September 2010, 03:57 PM   #14928
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Thank you stvnharr

What should be the best Jfet Idss for this app ?
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Old 11th September 2010, 04:23 PM   #14929
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Quote:
Originally Posted by 6h5c View Post
The input stage and output transistor are directly coupled, so any variation of the input stage current will have an effect on the operation point of the output transistor. The current source makes the operating point of the output transistor independent of the input stage. It will set the current to 10mA, whatever the input stage does.

I want to draw a new schematic anyway, so when do, i'll do some simulations with and without CCS, to see if there's less distortion.

Ray
Allready done, check THIS , Figure 15A/B/C and Table 3. And with 0.1mA through JFET's they don't know if they are barely alive or barely dead
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Old 11th September 2010, 05:46 PM   #14930
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Yep, that's also my conclusion, thanks for the link. I did some simulations today, and mainly the second harmonic is noticeably lower when using the FET current sink instead of the 1k8 resistor. Third harmonic was only just a bit lower. Current was set at 10mA, but if you use a trimmer in the current source, all options are open!

Ray
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