Jitter in DAC.

[rfbrw]

ghee0,
Implementing the Mark Levinson 'Intelligent FIFO', especially the latest version which generates the clock to the dacs using Direct Digital Synthesis and involves working with QFP surface mount packages would be a case of extreme diy. The AD1896 route would be much simpler. The only thing I would add to the previous posts on the use of the AD1896 is that you might want to consider reclocking the clocks to the PCM1704 with d-type flip-flops clocked directly from the crystal.

ray.

[Petter]

If you make the DAC master clock the master, you don't need to reclock. What you do is use an ordinary input receiver in the ordinary way, but now you feed the MCLK (master clock) directly to the DAC chip. It is usually the MCLK which the DAC chip is most sensitive to.

Then you take the master clock, modify if necessary (for example divide by 2 if necessary) and use that to drive the sources component.

Unless you are very unlucky with timing, you now have an almost optimal solution. For a FIFO to work, you need to have an amount of buffer (time buffer) in it unless you have Master type control over all clocks.

If you check out http://www.lcaudio.com and http://www.lcaudio.dk there used to be an article on how to do what I have described above.

If you want, you can add a FIFO where the input receiver controls the input clocking, and the master clock controls the output. This can deadlock though ....

If you want, you can forgo the input receiver completely by transmitting L/Rclk, bitpattern etc. from source without first converting to serial S/PDIF.

Petter

[rfbrw]

Petter,
My suggestion has nothing to do with the source components.
The point of reclocking or pipelining between the digital filter and the dac is that it goes some way towards removing any jitter generated in the filter. Slaving the transport to the dac is a completely different issue.
ray.

[richt]

hi petter

thanks for your info!

my dac is the master clock 33.868megs & is divided by 2
for the servo dsp.
but i made a very simple reshape with 74hcoo just purpose of
tesing & ive found that i was loosing too much information
due to a jittery clock!!!
ok i am thinking to install the master clock from lcaudio
but if the servo dsp that feeds the dac again is jittery
poor inprovment will be heard!
i want to reclock too all the info that comes from the dsp!
i need info
thank you

[walk]

Originally posted by Petter
If you make the DAC master clock the master, you don't need to reclock. What you do is use an ordinary input receiver in the ordinary way, but now you feed the MCLK (master clock) directly to the DAC chip. It is usually the MCLK which the DAC chip is most sensitive to.

Then you take the master clock, modify if necessary (for example divide by 2 if necessary) and use that to drive the sources component.

Unless you are very unlucky with timing, you now have an almost optimal solution. For a FIFO to work, you need to have an amount of buffer (time buffer) in it unless you have Master type control over all clocks.

If you check out http://www.lcaudio.com and http://www.lcaudio.dk there used to be an article on how to do what I have described above.

If you want, you can add a FIFO where the input receiver controls the input clocking, and the master clock controls the output. This can deadlock though ....

If you want, you can forgo the input receiver completely by transmitting L/Rclk, bitpattern etc. from source without first converting to serial S/PDIF.

Petter

[walk]

Hi !

I have some questions .

Maybe not correct , but I call the LRCK , BCK and DATA as I2S here - much shorter anyway .
Can qulity of I2S from the receiver/decoder in separate DAC
be better then ´´ the same ´´from dsp in transport ?

I use Sony cdp xa 50 es as transport only and SDS Labs tubedac as separate dac . Now I take the I2S ( three connections + ground ) from sony dsp and feed it straight to NPC SM 5843 filter in the dac. 16 MHz masterclock signal is only thing I get from Sony audioboard . Hopefully next week will get new 16 MHz clock from LCAudio , and I put it in separate dac close SM 5843 . Here is my next question .
How feed the dsp with 16 MHz clocksignal ? Now I see two
ways , like example on LCAudio homepage ´´Separate dac´´
and secondly use SM 5843 buffered CKO (pin 9 ) oscillator output , clock same frequency as XTI .

Tõnu

[tiroth]

Originally posted by hifiZen
So, I would go with the ASRC approach. Right now I'm building several test DACs for my big DSP project (which keeps getting sidetracked). All of the test DACs use either AD1892 combination receiver/ASRC or the AD1896, which is a superb sample rate converter.

If one is using AD1896 ASRC, is there any benefit (from the standpoint of jitter) towards feeding the ASRC directly from the DSP's SDATA/SCK/LRCK versus feeding it from a S/PDIF reciever?

I think I am in a similar position; I am planning using a DSP to do some processing on an incoming biphase or serial stream, so I can build the DAC to accept either (or both). However, if there is no difference to overall jitter when it is being passed through the AD1896 I see no reason not to include S/PDIF inputs, since they will make the DAC compatible with more hardware.

If you ever get anywhere on this DSP project I would be very interested in hearing about it. I currently have a TI C6000 demo board which is probably not ideal for this purpose, so I'd be interested in the SHARC approach, provided software and hardware is available out there. ^_^

[tttking]

I have made the XCLOCK modification to my DAC/Transport with very good result. Please check out the whole report in 'clock upgrade for cd/dvd players' Section of this Digital Forum.

[hifiZen]

tiroth:

That's exactly what I'm planning to build. The AD1892 includes the SPDIF receiver, while the AD1896 allows for 24 bits, and higher sample rates. So, the 1896 would typically be coupled with a separate SPDIF reciever IC. The beauty of using an ASRC is that it changes all input data into a single sample rate for your DSP. Thus, your filter coefficients and DSP filter structures can remain the same regardless of the input data rate. This is a wonderful simplification which also allows you to choose a sample rate on the DSP side to maximize your processor useage for best quality.

I am planning to have my first DSP hardware platform running about 6 months from now. It will be based on the ADSP-21065L, for 8ch input, 8ch output at 24 bit, 48 or 96 kHz (DSP sample rate). 4x SPDIF receivers, 4x I2S outputs to separate DACs / SPDIF transmitters. The host micro will be the Atmel ATmega103 - plenty of GPIO. I'll post updates as I make progress.

[Petter]

Just for clarification:

A recovered clock is likely to be less perfect than a master clock.

A high quality master clock near DAC chip as master clock is usually considered to be the optimal approach. You can source such clocks from for example valpey fisher as I did. IF you go for the master scenario you only need a regular unit. I got lucky when I called them since they usually only sell in large custom lots. Very nice people. Then again, there are other high-end communication companies doing oscillators + LC audio etc.

Petter