Jitter in DAC.

[ghee0]

Hi,

I am new to this. Anyway, I have a question in my mind.
I am going to built a audio DAC with a built in jitter attenuator. My question is, can I use a high speed FIFO and a low jitter clock to do it?

This is how I am going to implement. All the Bit, Data and L/R clks will be clocked into FIFO using recovered Master Clock [ from CS8414 ], and then the clocks will be clocked out from FIFO using a clean and low jitter oscillator. All the clocks will later feed into digital filter.

So, do you think this scheme will work?

What is the advantage of using FIFO over the convention method -> PLL?

Thank you.

[hifi]

maybe not an answer...but why dont you use Cs8420 with uppsampler....im currently building a dac with that chip a 3ps clock and cs43122, transformercoupled output..

i´ll get back with some results shortly...

/micke

[ghee0]

Hi Micke,

Thanks for the reply.

But the thing is that I have all the necessary parts already. PCM1704, DF1704, DIR1701 and etc. It is a bit too late for me to change the design and I want to go for 96KHz only.

Anyway, what is your source of your 3ps oscillator?

ghee0

[oweppe]

Hi ghee0,

I think that a FIFO can be used ONLY if you can control the source of the samples:

If you use separate clocks for read and write, they will have slightly different frequency :
If the reading clock is slower than the writing clock, the FIFO will sooner or later get FULL and you will lose samples.
If the reading clock is faster than the writing clock, the FIFO will sooner or later get EMPTY and the DAC will play wrong samples.

You need a control signal to tell the source when the FIFO is FULL or EMPTY
... this is not easyly done with a commercial transport.

oweppe

[ghee0]

Hi Oweppe,

You have a very good point here.

Actually, the read and write clocks are with the same frequency but different in timing and the amount of Jitter.

On the FIFO IC, there are "Almost Full", "Read Enable", "Empty" pins that I can use to control the flow of the clocks. In other words, the FIFO will start to clock out data when the "Almost Full" is enable until it sees a trigger on "Empty".

These pins will save me from lots of trouble, don't they?

Thank you!

ghee0

[hifi]

guido tent, i dont have his adress here but you can probobly search on his name....he got som god oscillators (integrated) and some VXCO:s

/micke

[ghee0]

Micke,

Do you mind sharing with us how your DAC circuit works? And what kinda IC you are using?

Do you implement a anti jitter circuity in your DAC?

ghee0

[hifi]

sure thing..if i get it to work =) i have borrowed heavily from http://www.diyaudio.de (dac4) i use his "adapter cards" but i have redrawen the "motherboard" i have exchanged the 7805 to Lm317...get rid of all otherstuff i didnt use...

yes the Cs8420 uppsampler with a 2.5->3ps clock takes care of jitter perfectly well....

the dac chips is Cs43122 (the latest and greatest from crystall) for outputstage i have jet to test some design but im leaning on just a passive one with lundahl transformers...

ohh by the way it is battery powered...separate supplyes for digital and analog...and about 0,1-2F in total capacitance......

/micke

[arnach]

In response to an earlier post, the Mark Levinson DACs use a FIFO to kill jitter. They have standard I/O that can be used to with regular transports. So no modifications to the "commercial transport" then?

--arnach

[ghee0]

Can anyone tell me how to properly implement an anti jitter circuit with a FIFO?

For instance, how Marklevinson reduce jitter in their DACs?