External reclocking and error due unequal input data and clk freq.

[andy2]

Hello,

When using an external clock for reclocking, there might be slight mismatch between the input master clock and the input data stream. Therefore occasionally, a stereo sample pair has to be reread or dropped depend on which freq. is faster.

Does anyone know how this affects the sound?

[Ulas]

It’s audible as a soft “tht” sound.

[bitrate]

Hi!
In my opinion external master clock used to reclocking MUST be synchronized with data clock (PLL circuit).How this will sound depends from length buffer memory which you use.You can also try ASRC but this will only 'glue' input jitter to datastream .
Regards
Martin

[andy2]

Originally posted by bitrate
Hi!
In my opinion external master clock used to reclocking MUST be synchronized with data clock (PLL circuit).How this will sound depends from length buffer memory which you use.You can also try ASRC but this will only 'glue' input jitter to datastream .
Regards
Martin

If you use external clock then there is no way to synchronize. The only way to synchronize is only if the clock phase and freq. get changed by the digital receiver (such as CS8412), but if you allow the receiver to change the clock then it sort of defeats the purpose of using external clock in the first place.

If you look at some of the schematics that use external clock, the master clock pin of the CS8412 is configured as an input and the same clock is used to clocked the data into the DAC.

I was reading the AD1896 and it seems like it uses ASRC by interpolating the input samples based on the external clock. I am not sure if this is supported by CS8412.

[bitrate]

When I wrote about reclocking circuit , I thought about this :


In other case You you have to send clock signal back to the transport ,due to proper synchronism.
Regards
Martin

[bitrate]

Image which I Attached is not avilable Anyone know Why?

Nevermind ,You can see it here:
http://img60.exs.cx/img60/7831/reclock5lq.jpg
Regards
Martin

[andy2]

Originally posted by bitrate
Image which I Attached is not avilable Anyone know Why?

Nevermind ,You can see it here:
http://img60.exs.cx/img60/7831/reclock5lq.jpg
Regards
Martin

Bitrate:

I am still not sure if it will suppress jitter.

Let say the MCLK coming out of the CS8412 has jitter. This clk is used to lock the MCLK_out which in turn clock the data out of the FIFO. I guess the goal here is to minimize the jitter of MCLK_out.

Since MCLK is still jitter which is about 200ps as quoted on the data sheet, MCLK_out would still be jitter also.
But I supposed MCLK_out jitter would be minimized and less than that since it is phase-locked to MCLK.

And of course, the output path of the FIFO to the DAC is very small so jitter would be minimized also.

[bitrate]

The advantage of using this circuit (PLL based) ,is one thing : PLL converting jitter (phase noise) into voltage noise (or digital noise in ADPLL) which can be filtered (in loop filter).In good PLL designs jitter reduction ratio is about 100.
More about PLL You can find here:
http://httpd.chello.nl/~m.heijligers...l/PLL/PLL1.htm

My favourite example :
http://focus.ti.com/lit/an/scaa067/scaa067.pdf
See page 5
Regards
Martin


Ps.Sorry for my poor english

[oehlrich]

Originally posted by bitrate
The advantage of using this circuit (PLL based) ,is one thing : PLL converting jitter (phase noise) into voltage noise (or digital noise in ADPLL) which can be filtered (in loop filter).In good PLL designs jitter reduction ratio is about 100.

I studied the datasheet of th AD1896 ASRC. It has an internal digital servo loop (2^20*Fs) and a FIFO so jitter will be reduced to a maximum of 5ps!! The rejection starts at 1Hz. To reduce the long lock in time the unit has a fast mode which is used before it switches to slow mode.

Result really sounds great. I tested it with my ears on signals showing a different kind of jitter. Some signals I used were so bad that I could clearly see the jitter in the eye-diagram (+- 10%). At the output of the unit you really hear NO difference between signals with or without jitter!!

Beyond this the advantage is you could use a extremely low jitter oscillator (no PLL or VCXO) to clock the output stage of the AD1896 and the D/A.

In my opinion the AD1896 is the best chip to forget about the jitter problem.

Charly