reclocking circuit

[ackcheng]

Does anyone know why this reclocking circuit need to clock frequency

One of 33.8688 and the other one form the clock of CDplayer?

[rfbrw]

It is an attempt to reclock the SPDIF datastream and it is not a good idea. While the 33.8688MHz clock will be in sync with the clock and data part of the datastream, it will be out of sync with the the code violations that form the preambles. Whatever effect it may have, I doubt it will be for the better.

[Jocko Homo]

Trying to use all the inverters in the chip will increase jitter. Not to mention AC logic. At least they are not using the Q-bar to make a "balanced" output.

Jocko

[JohnW]

rfbrw,

Are you sure what you say is correct - this would imply that the preambles are async. to the master clock - which I believe is incorrect.

However, I'm not sure what you mean by "out of sync with the code violations that form the preambles"

Circuits I've seen of DOTX circuits appear to have been always latched to the master clock - but then I didn't look that closely and could have missed something.....

Ackcheng,

The circuit provides the Master clock to the CD servo chipset.

John

[Fin]

But why have they used so many of the inverters in this IC?

[JohnW]

I’m being very slow today – the DOTX is must defiantly Synchronous to the system Master Clock.

As Fin rightly questions, the circuits fatal error is the sharing of the Clock buffers (U1 1/6 & 2/6) with the DOTX output buffers (U1 3/6 & 4/6), phase noise from the DOTX buffers will cross modulate the Clock buffers – making the circuit useless.

I’ve found that VHC and UHC logic extremely good for phase-noise – but ONLY when ONE gate is used per package. The best by a long shoot is Fairchild’s UHS single Gate logic NC7SZ74 etc operating at 5V (I operate them at 6V to squeeze that last dB out of them).

I’ve built discreet DAC’s using UHS Single Gate logic with dynamic ranges of greater then 132dB – limited by the measurement equipment I guess. To achieve this level of dynamic range means the inherent Phase Noise of this logic family must be very low.

Fin – will answer your pending questions ASAP.

Cheers,

John

[ackcheng]

Dear John and many others

Can you point me to a site / resources on the internet that shows what you think is a good reclocking circuit?

[Jocko Homo]

Take out all of the inverters. Don't use AC logic.

All the circuits on the web that I have seen are lousy. Same flaws as this one.

You can't let DC flow through the core, it will saturate. The resistor values may need tweaking. Might benefit from a zobel network. With that lousy transformer....my guess would be something between 27 and 39 pF should work.

(I have 'splained this before...............)

Jocko

[Fin]

Originally posted by JohnW
As Fin rightly questions, the circuits fatal error is the sharing of the Clock buffers (U1 1/6 & 2/6) with the DOTX output buffers (U1 3/6 & 4/6), phase noise from the DOTX buffers will cross modulate the Clock buffers – making the circuit useless.

Looks a bit like the setup in the Arcam Delta.
Ackcheng - I can send the schematic to you but it is not ideal either.

Originally posted by JohnW
I’ve found that VHC and UHC logic extremely good for phase-noise – but ONLY when ONE gate is used per package. The best by a long shoot is Fairchild’s UHS single Gate logic NC7SZ74 etc operating at 5V (I operate them at 6V to squeeze that last dB out of them).

Do you know of anything similar in DIP packages.

Originally posted by JohnW
Fin – will answer your pending questions ASAP.

Thanks John!

[Jocko Homo]

Nope. All that stuff is in teeny tiny SM packages. But if a blind old git like me can build stuff with them..............


Jocko