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Old 3rd March 2005, 01:48 PM   #1
borges is offline borges  Norway
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Default S/pdif

I need to learn more about S/PDIF and I2S. Where can I find presentations and intros online?

By the way, is it aii-squared-ess or aii-two-ess?

Greetings,

BÝrge
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Old 3rd March 2005, 03:57 PM   #2
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IIS - Inter IC Sound bus.
http://www.semiconductors.philips.co...ous/I2SBUS.pdf
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Old 3rd March 2005, 09:13 PM   #3
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Default Re: S/pdif

Quote:
Originally posted by borges
I need to learn more about S/PDIF and I2S. Where can I find presentations and intros online?

By the way, is it aii-squared-ess or aii-two-ess?

Greetings,

BÝrge

skwerred
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Old 4th March 2005, 06:52 AM   #4
borges is offline borges  Norway
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Default Re: Re: S/pdif

Quote:
Originally posted by Guido Tent



skwerred

Thanks Guido. Didn't know you were an ornithologist, I could bet that's the scream of the Dutch Great Owl


Greetings,

BÝrge
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Old 4th March 2005, 08:31 AM   #5
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Default Re: Re: Re: S/pdif

Quote:
Originally posted by borges



Thanks Guido. Didn't know you were an ornithologist, I could bet that's the scream of the Dutch Great Owl


Greetings,

BÝrge
Hello BÝrge,

Actually, I am not an ornithologist, but I tried something fonetically most close to squared......

cheers
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Old 4th March 2005, 08:53 PM   #6
borges is offline borges  Norway
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Hi Guido,

There is one thing I wonder about when it comes to I2S. In a previous post of mine I was asking which clock is most critical to a BB PCM1704 and friends.
(Here's the thread.) The MCLK (256x44.1kHz) came out as the winner.

Do you know how much jitter can be tolerated on this 11.2896MHz clock before it gets audible? Well, in our line of work there is usually no such thing as a lower or upper bond to things. But still, would for instance 50ps RMS jitter be bad? What can you achieve with a carefully designed clock circuit?

I'm asking because I plan a new DAC board and can't quite make up my mind as to how I should arrange the MCLK.


Good night/weekend!

BÝrge
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Old 4th March 2005, 09:22 PM   #7
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Quote:
Originally posted by borges
Hi Guido,

There is one thing I wonder about when it comes to I2S. In a previous post of mine I was asking which clock is most critical to a BB PCM1704 and friends.
(Here's the thread.) The MCLK (256x44.1kHz) came out as the winner.

Do you know how much jitter can be tolerated on this 11.2896MHz clock before it gets audible? Well, in our line of work there is usually no such thing as a lower or upper bond to things. But still, would for instance 50ps RMS jitter be bad? What can you achieve with a carefully designed clock circuit?

I'm asking because I plan a new DAC board and can't quite make up my mind as to how I should arrange the MCLK.


Good night/weekend!

BÝrge

Hi

I still hear improvement going from 20 ps to 3ps on that PCM1704 BCLK

My TentLabs clocks have about 3 ps rms (10Hz-20kHz)

Currently I am working on a redesign of a CD player of a mid size high end company, using the 1704 and my clocks. The results are very promissing.

best regards
-
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Old 4th March 2005, 11:07 PM   #8
borges is offline borges  Norway
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Quote:
Originally posted by Guido Tent

Currently I am working on a redesign of a CD player of a mid size high end company, using the 1704 and my clocks. The results are very promissing.

best regards
-
Glad to see other nightbirds out there. This sounds a lot like the undertaking I plan. I'll put a good clock next to some 1704s, buffer it and run the CD drive from there. But 3ps, that is impressive. How do you measure it? Can scopes capture that at all?

However, I'm also going to use a somewhat uncommon I2S source (more on that later) which I cannot sync from a clean clock. Do you know how close one can come to your clock specs with a PLL or perhaps even narrow-badwidth filters strapped to the CS8414?


Greetings,

BÝrge
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Old 4th March 2005, 11:48 PM   #9
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Quote:
Originally posted by borges
Do you know how close one can come to your clock specs with a PLL or perhaps even narrow-badwidth filters strapped to the CS8414?

Guido will probably suggest this:-

http://httpd.chello.nl/%7em.heijlige...tml/dactop.htm


And this thread might help as well:-

Tcxo
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Old 5th March 2005, 12:22 AM   #10
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"Strapping narrow-bandwidth filters" on a '841x won't get you anywhere near that close. You will still be 2 orders of magnitude off. If you use a secondary PLL, like one of you-know-who's, you will get essentially the same level of performance as a good clock.

No, you can't measure it on a 'scope. But trust, me.......something like a '1704 will not sound right unless the clock is very good.

Jocko
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