Does the CS8412 input I2S?

[Kip]

I want to use a I2S input instead of the the SPDIF input. If it is possible what pins? I am using a TDA1545a chip that needs a EIAJ input. I want to go from a I2S to EIAJ. I bought this kit

[blu_line]

as far as i could conclude from the datasheet, it will convert from SPDIF to IIS only !

You can take an CS8420 instead !

grtz

Simon

[Kip]

So the CS8420 will input a I2S from my CD-PRO2M kit and output EIAJ for the TDA1545a chip?

[DragonMaster]

If you use the circuit here

Sony to Philips I2S Format Conversion

but invert it?

[apollyon25]

Using the above linked circuit will NOT convert SPDIF to IIS.

Spdif is a serial format with embedded clock and protocol information contained within the serial data. IIS is a different sort of 'serial' format. There are two clocks - BCK, a bit clock, to clock each bit of the signal in, LRCK, to determine if the data is left or right channel information, and DATA the data.
The data has no packet information, or error correction. It is pure music information data for both channels.

You will need a protocol adaptor. Look at AKM (Asahi Kasei) semiconductor, they make several types. A DIR is the input (SPDIF to IIS) transceiver, the DIT is the output (IIS to SPDIF) transceiver.

Hope this helps,

apollyon25

[DragonMaster]

He wants I2S to EIAJ, no SPDIF. I2S and EIAJ just have different timing.

[Kip]

I2S to EIAJ circuit it what I need. DragonMaster has it right, but I don't know how to design a circuit or invert the one shown. I will need a schematic and parts list.

[DragonMaster]

I think using the delay for DATA instead of LRCK will work.(In the scheme, exchange pins 2 and 3 at the input, and at the output the 3 different delayed WS will be DATA instead and DATA will be LRCK/WS)

I can't tell if it will work, try it or ask CM.

(BCK could have to be inverted . . .)

[DragonMaster]

Oops, the link I told wasn't the same thing:

Sharing all my digital work - will downloaders pay to maintain diyaudio?

I2S.ZIP

[rfbrw]

I2S data is near enough MSB justified. The TDA1545A expects LSB justified data. Aside from inverting WS, FSYNC,WCLK, LRCLK or whatever name it goes by in your setup, you have to delay the data by 15 bitclock cycles.