CS8412 + filterless Non-OS dual AD1865

[cathode_leak]

I've been alot back and forth on my DAC project, and finally I have made up my mind and there is no turning back now. Chips are already on their way, and they are the highly raved AD1865..

Now, I would like to implement these in balanced config, one chip driving each channel, and if I've got my glue logics right (wich I never do ) one '86 quad xor gate (look at the far right of the attached schematic) will perform this task (hopefully). As I'm a totally fresh newbie in CMOS logic, I'd really really appreciate comments and corrections on the AD1865 logic interface.

The SPDIF front end for the CS8412 reciever is a balanced setup using 74HCU04 unbuffered hex inverter for gain, and a 74HC86 XOR gate for driving the tranny balanced.. Jocko spent some big effort trying to explain me how to do a TX reclock, but I did not get it. I will, however, do a reclock of the I2S signal, and are looking for advice;

The clock/counter circuit in the upper left corner of the schematic shows what I imagine would be a flexible and high-speed solution capable of delivering an Fs of 44.1KHz, and multiples up to 1024Fs (@45MHz).. but my thoughts on flexibility isn't really that much of a matter as I know nothing about clocking...

I wonder; how will I best incorporate reclocking into this circuit? In non-OS designs on the net I've seen clocks running from bin counters right onto FSYNC and SCK, I've seen '74 flops being used as for example in Pedja Rogic's implementation of a kwak clock in his 1541 dac, but I have no idea about pros and cons for the different methods of reclocking... Also, should the DATA/SDATA line (the line containing the data stream) be reclocked? The only thing I am sure about; Clock will have to be a Tent XO. No VCXO. only XO. And no $500 clock modules, I will run the stuff of batteries so an XO will do.

My apologies for the wide and thin schematic, let's hope you guys have big flashy widescreen 'puters The schem is simplified, it does not show power connections, but I intend on using a bunch of TL431 shunts for this purpose. I/V conversion will be passive as the schematic suggests...

EDIT: some other circuitry like the M0-M3 mode select of the 8412 is also missing from the schem. they will probably be jumper programmable.. But it's of less importance really as long as I put it in right mode

[philbyx]

Hello

I think that the cd4040 will not work at 40 MHz.

Did you see my own project on ad1895 and reclocking ? :

http://www.diyaudio.com/forums/showt...767#post554767

Philippe

[cathode_leak]

Most interresting.. If I may ask, what are the reason for the 56 ohms resistors in your circuit (tying together reciever/logics and dacs)

Any special reason for your choice of clock frequency?

Proly a stupid question, it wouldn't be my first on this forum , but any special reason not to reclock the system clock of the chips? (SCK, BitClock, CLK, whatever we call it)

Regarding your DIY build; how do you like it? how does it compare to other chains if you've had the chance to compare? concidered using a tube buffer?

Originally posted by philbyx
I think that the cd4040 will not work at 40 MHz.

But another 4040 like the 74HC4040 will won't it?


EDIT:
The two hex inverters on the attached pic performs the same job, no? any reason for not using just one, and wiring DL to DL1? (I'm asking because the latter is what I've drawn in my circuit exept I use xor not invert, but then again I used xor to invert )

[Jocko Homo]

You want to use a Tent XO, but not a VCXO. Once again, you miss the entire point of what reclocking in a DAC should be about.

Go ahead.........use ACT logic.........[joke]

Since you are a newbie, why do you want to design your own, when need to learn how it all works first? There are enough designs already here for you to copy and learn from. Your time would be best spent doing that, the conjuring up things that have little chance of working.

If you lived stateside, I would give one to copy, but................

Jocko

[gmarsh]

You're not reclocking, you're resampling a clock with an asynchronous clock!

Assuming you have infinitely fast edges and don't run into any metastability issues or dropped or double-counted clocks... then you will have created an *unbelievable* amount of jitter in your resampled clock. If you look at it on a scope, you'll see your clock smeared all over the place... And any sort of beat frequency created between your sampling clock and your CD player clock might even create spurious tones in the audio band.

If it works, it'll sound like garbage. If it doesn't work, well, it'll either sound like complete trash or it will sound like nothing.

You need to do synchronous resampling. Pull that Tent clock out of there, and replace it with a low-jitter, VCXO-based PLL which tracks the clock output of the CS84xx and generates its own low-jitter clock output.

[cathode_leak]

Originally posted by gmarsh
You're not reclocking, you're resampling a clock with an asynchronous clock!

Assuming you have infinitely fast edges and don't run into any metastability issues or dropped or double-counted clocks... then you will have created an *unbelievable* amount of jitter in your resampled clock. If you look at it on a scope, you'll see your clock smeared all over the place... And any sort of beat frequency created between your sampling clock and your CD player clock might even create spurious tones in the audio band.

If it works, it'll sound like garbage. If it doesn't work, well, it'll either sound like complete trash or it will sound like nothing.

You need to do synchronous resampling. Pull that Tent clock out of there, and replace it with a low-jitter, VCXO-based PLL which tracks the clock output of the CS84xx and generates its own low-jitter clock output.

What are you talking about? I have not even decided on how to reclock... And you are telling me it won't work??

I asked for advice for reclocking this circuit, but cannot see how you can make your conclusion by only knowing I want to use a battery powered XO-1 clock?

Are they really that bad? If you read my post, you'd see that the clock circuit in the schematic is in no way intended to be put into the rest of the circuit. It was just a suggestion, but as I said; I dunno much about reclocking... that's why I asked for advice...

[Jocko Homo]

And two of us now have given it to you. Just becasue you don't like the answers doesn't not make them incorrect.

Yes, they are that bad. I have tried to be nice, I have even sent you e-mail. If you insist on banging your head against the wall, well, we have warned you.

Jocko

[cathode_leak]

Originally posted by Jocko Homo
Since you are a newbie, why do you want to design your own, when need to learn how it all works first?

That retoric question holds it's own answer doesn't it? to learn how it all works.. but hey, why don't I just buy my audio gear at the nearest hi-fi pusher? I suppose I could, but I dunno what there is to learn from it... exept that most pushed hi-fi gear sux unless you pay $$$. No I am not going to buy a kit to solder the components in place. I do not find soldering that amusing.

[Jocko Homo]

Hmmm......spell check works.........they need to invent grammar checks, too. Oh well.......

No, I am not suggesting to buy a kit. Copy something that works, instead of trying design stuff way over your head.

If you do not understand that logic gates do not work off of SPDIF level, then don't try to design something. And stay away from any attempt at reclocking on the RX side. Unless you are buying a ready made secondary PLL.

Even I buy them already made, because it saves time in small quantities. If I was still selling D/A boxes, then I would design my own. But I don't.

Reclocking on the TX side is easy........you have already invented it more times than you know with your attempts to make a SPDIF RX.

I don't find soldering amusing either. Which is why I don't build something unless I know it will work properly the first time.

Jocko

[cathode_leak]

Originally posted by Jocko Homo
And two of us now have given it to you. Just becasue you don't like the answers doesn't not make them incorrect.

Yes, they are that bad. I have tried to be nice, I have even sent you e-mail. If you insist on banging your head against the wall, well, we have warned you.

Jocko

Jocko, first of all, I appreciate the time you have spent trying to explain the SPDIF, but it's not easy for a newbie to gather the shreds of pieces of information you supply.. "Do a reclock at the TX side and at the RX side"..."Get rid of the TX reclocking"..."74 cannot produce balanced out".. but hey, check that Qbar output!! I am sorry I asked in the first place.. You've spent a lot of effort leaving clues to complex for me to understand, but not one second trying to explain how and why in an understandable way. Possible because you do not want to give your "secret tricks" away without being paid, but that's not much of a DIY spirit.. I realize you are quite competent within the subject, but that doesn't help me squad. That single picture Elso posted actually told a whole lot more of a usable setup than the clues you left behind...

Originally posted by Jocko Homo
If you do not understand that logic gates do not work off of SPDIF level, then don't try to design something.

That is learning for me... I realized 0.5V will not trigger CMOS logic.. but looking stuff up, I see one can build a buffer that will give gain enough to enable use of CMOS, for instance using a 74HCU04 or a comparator.. Useful. Regarding the logics... OK, I have not been into CMOS electronics before, but I'm quite familiar with assembler language so NOR ROR ROL XOR OR AND NEG etc are not new terms to me. It just took some time to realize how they actually were put to use in electronics... Again, the result is learning...