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Old 10th February 2005, 01:49 PM   #1
borges is offline borges  Norway
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Default pcm1704: Jitter on WCLK

The datasheet for the Burr-Brown pcm1704 says that

"The serial-to-parallel data transfer to the DAC occurs on the falling edge of WCLK. The change in the output of the DAC occurs at the rising edge of the 2nd BCLK after the falling edge of WCLK".

Does that mean I can have a jittery (as in generated by async or poorly PLL'ed FPGA) WCLK as long as BCLK is nice? I respect all setup and hold time specs when I interface the converters.


Greetings,

BÝrge
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Old 10th February 2005, 02:03 PM   #2
philbyx is offline philbyx  France
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Quote:
The change in the output of the DAC occurs at the rising edge of the 2nd BCLK after the falling edge of WCLK
Nothing to do with the falling edge of wclk. The important is bclk only.
wclk can be jittery, it's a rising edge of bclk which have te be at time without jitter.

Some Dac (ad1865 for example) need a perfect wclk, because it is the falling edge of wclk which transfers the datas from the shift register to the parallel register of the dac.

But in your case, best effort on bclk.

Philippe
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Old 10th February 2005, 09:56 PM   #3
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Quote:
Originally posted by bÝrge


The datasheet for the Burr-Brown pcm1704 says that

"The serial-to-parallel data transfer to the DAC occurs on the falling edge of WCLK. The change in the output of the DAC occurs at the rising edge of the 2nd BCLK after the falling edge of WCLK".

Does that mean I can have a jittery (as in generated by async or poorly PLL'ed FPGA) WCLK as long as BCLK is nice? I respect all setup and hold time specs when I interface the converters.


Greetings,

BÝrge

Ummm, it seems philbyx's datasheet for the PCM1704 differs from mine. In the datasheet I have, WCLK determines the transfer of data into the parallel register and thus conversion i.e. WCLK reflects the sample rate the dac is running at. Furthermore, according to my datasheet, BCLK for 24bit/44K1 data can vary between 8MHz and 11MHz and can be stopped altogether such that it is not running when conversion takes place. Now, I don't have much time for all this clock fetishism but I would focus my efforts on WCLK.
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Old 11th February 2005, 04:17 AM   #4
BrianL is offline BrianL  United States
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Why argue about datasheets? Just go to www.ti.com and
download the latest and most up-to-date-est.

It is clearly defined on page 7 as Borge quoted.
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Old 11th February 2005, 05:10 AM   #5
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Originally posted by BrianL
Why argue about datasheets? Just go to www.ti.com and
download the latest and most up-to-date-est.

It is clearly defined on page 7 as Borge quoted.

It isn't about the datasheet. It is about whether WCLK is more important than BCLK. As WCLK triggers conversion and BCLK need not be present at conversion, I maintain that WCLK is more important than BCLK.
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Old 11th February 2005, 06:21 AM   #6
philbyx is offline philbyx  France
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Hello Rfbrw

Two minutes ago, I went to TI focus.

I put the timing diagram below in my post.

It's quite obvious that Bclk will synchronize the analog part of the Dac.

The Dac output will be changed by Bclk.
Wclk has a only internal effect (loading of intermediate registers I think) and the Jitter on it has no effect on analog output rythme.

Philippe
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Old 11th February 2005, 07:57 AM   #7
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Quote:
Originally posted by philbyx
Hello Rfbrw

Two minutes ago, I went to TI focus.

I put the timing diagram below in my post.

It's quite obvious that Bclk will synchronize the analog part of the Dac.

The Dac output will be changed by Bclk.
Wclk has a only internal effect (loading of intermediate registers I think) and the Jitter on it has no effect on analog output rythme.

Philippe

Hi

As I read it, this is correct, I rephrase the datasheet

" The change in the output of the DAC occurs at the rising edge of the 2nd BCLK after the falling edge of WCLK "

It is also my experience when applying the 1704, bck is very sensitive.

However, internal crosstalk may affect the bck jitter, so I suggest to reclock all digital signals entering the 1704. At least in the DCA we designed using the 63 it helped.

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Old 11th February 2005, 08:06 AM   #8
philbyx is offline philbyx  France
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Hi Guido

Quote:
At least in the DCA we designed using the 63 it helped.
I don't understand what you mean .

Philippe
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Old 11th February 2005, 09:09 AM   #9
borges is offline borges  Norway
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I have worked with the PCM1702 before. That one latched on the 4th BCLK after WCLK. (I know because I had a sample and hold circuit on the same board. Don't ask why...)

The PCM63 was the predecessor of the PCM1702 if I got this right.

In my setup, there is an FPGA which uses its own async clock. I pick the 11MHz from the cd player, buffer it there with a 74HC04, and feed it directly to BCLK on the DAC. The FPGA polls BCLK so that it knows what do do with with SDATA and WCLK.

The reason I didn't reclock SDATA and WCLK was that I wanted to avoid excess circuits and noise sources at the critical 11MHz. Rather, I thought the async FPGA clock would spread any noise coupled from those signals over frequencies that are not harmonic products of my sample rate.

Statistically, this should give the arrival time of a WCLK or SDATA edge a flat distribution which is 10ns long. Relative to a BCLK edge, that is. (Because of the async 100MHz clock of the FPGA.) Comments?

I know the '04 buffering of the CD player clock is not the best idea ever. Next addition is to put a nice clock on the analog board, close to the DACs, buffer it and run the CD player transport off that. (I'll be starting a new clock comparison thread when the time is right!)


Greetings,

BÝrge
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Old 11th February 2005, 12:30 PM   #10
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Quote:
Originally posted by philbyx
Hello Rfbrw

Two minutes ago, I went to TI focus.

I put the timing diagram below in my post.

It's quite obvious that Bclk will synchronize the analog part of the Dac.

The Dac output will be changed by Bclk.
Wclk has a only internal effect (loading of intermediate registers I think) and the Jitter on it has no effect on analog output rythme.

Philippe

And there we must disagree. You think the diagram shows instantaneous conversion on the rising edge of the second BCLK after WCLK. I, OTOH, think it shows conversion triggered by WCLK and the output occurs on the rising edge of the second BCLK after WCLK. i.e conversion time is around 34nS. Experience and the NPC and TI/BB datasheets tell me that BCLK need not be present at the time of conversion and if it isn't there, it can't trigger anything.
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