Balanced SPDIF reciever?

[cathode_leak]

I am messing around with the Crystal CS8412 digital reciever chip, trying to build a decent SPDIF input stage for it and realizes this task is not as trivial as it first appeared to me...

After reading through an informative thread on the subject, I could not help myself from stopping again and again reading through WMS's post at http://www.diyaudio.com/forums/showt...7860#post27860. This definitly looks like the way to go, and the 6111 triode idea melted me.... My bet will, I think, be to use the 74HC86 (or VHC) wired as a phase splitter for the digital signal, using a 6111 dual triode pencil tube to amplify both phases into an Aes-EBU transformer...

Now, when using the 6111 tube in place of transistors as WMS suggests, I would have to set it up as cathode follower with coupling capacitors wouldn't I?

Also, Partsconnexion has a Aes-EBU-tranny that might be a good alternate to the Lundahl LL1566 I have, since it appears (judging by it's picture, i have to check this) to have centertap on its primary, wich might be beneficial to connect to ground reference in a balanced scheme?

Could anyone help me get somewhere with this? Any thoughts or ideas? Here is a copy of the circuit MWP suggests, but using transistors...:

[Jocko Homo]

Why do you think that you need to amplify it? The output is supposed to be 0.5 V p-p, not 50 V p-p.

Jocko

[cathode_leak]

Originally posted by Jocko Homo
Why do you think that you need to amplify it? The output is supposed to be 0.5 V p-p, not 50 V p-p.

Jocko

True, but the output of the 74HC86 OR-gate is hardly 0.5V p-p is it? I'm not an expert on this digital stuff but I had the impression it was much lower.. Are you saying a 74xx86 chip can drive the tranny on it's own? and wouldn't the signal benefit from a buffer (with regards to reflections, etc) even if the buffer provides only minimal gain?

Edit: Also, the CS8412 chip will have no problems handling a higher, say 3V p-p signal (example out of the blue), with it's self-biasing feature?

[cathode_leak]

Apparently, Harry have had good experiences using the '86, so I thought it was a somewhat safe and way easier approach than reclocked flipflop or other suggestions i've seen.. Here's what he says;

Originally posted by HarryHaller
I have used the 74HC86 as a phase inverter for driving balanced digital out for AES/EBU interfaces. It works real well. Jocko said this circuit was too good to give away for free!

[Jocko Homo]

Uh..........the output is CMOS level..............5 V p-p. You need to reduce it, not amplify it.

As for reclocking F-F..........put it in front of the '86, and only use one ouput. Yeah, too good to give away for free, but what the hey............

Don't use the Lundahl. They make good audio transformers, but SPDIF onrs are totally different. I would not use them. Or any designed for AES-SPDIF conversion. Or 2:1 ones, either.


Jocko

[cathode_leak]

Thanks for your reply, Jocko.

Originally posted by Jocko Homo
Uh..........the output is CMOS level..............5 V p-p. You need to reduce it, not amplify it.

Aah... I see... Then why would WMS use transistors in his example schem? Reducing voltage can be done purely resistive...?! He uses them to battle impedance transients of the '86 rise fall? could I use a no-gain OPA627 buffer for this purpose? (627s are probably overkill but I have spare chips laying around)

As for reclocking F-F..........put it in front of the '86, and only use one ouput. Yeah, too good to give away for free, but what the hey............

Is there any obvious advantages of reclocking in the input stage instead of say, between the digital reciever and the DAC? pros & cons?

Don't use the Lundahl. They make good audio transformers, but SPDIF onrs are totally different. I would not use them. Or any designed for AES-SPDIF conversion. Or 2:1 ones, either.

Are you suggesting to use no transformer at all? I do in fact have a pair of very small chip trannys that, AFAIK, are not the "scientific aes/EBU".., 1:1, chinese production marked "PE-65612", "0203-C".. IIRC they were designed for digital signal transmission, would they be the better choice than "standard" Aes/EBU?

Edit: PE-65612 pdf @ http://www.elfa.se/pdf/56/05655055.pdf

edit: edit: BTW they are pulse trannys...

[cathode_leak]

Originally posted by myself
could I use a no-gain OPA627 buffer for this purpose?

I just realized it would be a very stupid thing to waste OPA627s in a buffer with no gain.. I'll rather ask wether OPA2134 could be a suitable buffer... got spares of these too...

[Jocko Homo]

Yes, he wants to keep the impedance constant, but I bet that he does not have a TDR. I do...........

I never tried adding a follower, but then I have other ways of isolating the driver from the line.

Those cheap Chinese transformers are ok. A cheap version of a Schott, that was good. Lundahl............stick with his audio transformers.

I would not waste a good part of the SPDIF output. It has to work at 2.8 MHz, and pass at least the fifth harmonic.

Still want to use a good audio part there??????

Yes, reclock on the TX side. On the RX side, you need to come up with a seconadary PLL, and use that to get the recovered clock.

(I have a buddy that sells one, but it is not cheap. I use one, but I need a good reference system.)

Jocko

[cathode_leak]

Originally posted by Jocko Homo
Yes, he wants to keep the impedance constant, but I bet that he does not have a TDR. I do...........

I never tried adding a follower, but then I have other ways of isolating the driver from the line.

The logic question would be "how", now wouldn't it? And one other thing... I don't have a TDR either I believe.. but I could not be sure because I have no clue what it is. What does it tell you? Measurements are better for your line isolation tricks than for op-buffer?

Those cheap Chinese transformers are ok. A cheap version of a Schott, that was good.

Good. Then I will work with the chinese trannys for now, and concider upgrading them at a later point.. Thanks for the tips

Yes, reclock on the TX side. On the RX side, you need to come up with a seconadary PLL, and use that to get the recovered clock.

Whow, I'm getting an overdose of digital language Let's assume for a second that my setup will be the reclocked 74 flipflop, into the 86 as digital phase splitter, resistive network, opamp buffer, then the tranny...

Would I feed the 74 on the TX side 2.8MHz, and then 44.1KHz for CS8412 FS output on the RX side? If so, could this be done as simple as using one clock, say 11.289MHz, and use a binary counter or other suitable logic to divide by 4 and 256?

Sorry if I ask very dumb questions here.. New*cough*bee

[Cobra2]

Originally posted by cathode_leak

Good. Then I will work with the chinese trannys for now, and concider upgrading them at a later point.. Thanks for the tips

Unless the world has a "back-spin", you will probably not find any better trafo, just as with transports/lasers and dinosaurs...

Arne K