Undershoot in Kwak clock 7

[Niklas]

Hi!
I ha ve just implemented a Kawk clock 7 on a home made PCB.
In my measures I experience a "big" undershoot and some "ringing" in the low cycle.

What is causing the undershoot?
Is this due to a design error from my side or is it supposed to do that?
If it is error, any idea where the error might ?

How about rise and fall times? i measure appr. 2 ns fall time and 6 ns rise time (22.5792MHz oscillator). Is this a trimming issue?

I will try to get some printout from my measure if it would help.


Thanx!

//Niklas

[Elso Kwak]

Originally posted by Niklas
Hi!
I have just implemented a Kwak clock 7 on a home made PCB.
In my measures I experience a "big" undershoot and some "ringing" in the low cycle.

What is causing the undershoot?
Is this due to a design error from my side or is it supposed to do that?
If it is error, any idea where the error might ?

How about rise and fall times? I measure appr. 2 ns fall time and 6 ns rise time (22.5792MHz oscillator). Is this a trimming issue?

I will try to get some printout from my measure if it would help.


Thanx!

//Niklas

Hi Niklas, Don't worry too much. The ringing may be due to the measuring setup. Even the duty cycle adjustment is not critical as only the rising edge is used by then CDP.

[Niklas]

thank you Elso!
Then I don´t have to worry =)

//Niklas

[Guido Tent]

Originally posted by Elso Kwak

Hi Niklas, Don't worry too much. The ringing may be due to the measuring setup. Even the duty cycle adjustment is not critical as only the rising edge is used by then CDP.

Hi,

If it is due to the setup, you should see symmetrical ringing. Otherwise it is due to the circuit.

This does not implicate it is bad but I see it more often, for example due to asymetrical output impedance.

By the way, some converters convert at the falling edge. I've seen DACs where the jitter on the falling edge was significantly higher than on the rising edge......

best regards
-

[finneybear]

Now this is interesting. Which audio DAC is working on the falling edge of clock? Just curious. Most modern DACs have OSC inside synched with the external reference clock. It's odd that the internal OSC would synch with falling edges.

Anyway, rising edge, falling edge, the 2ns and 6ns setup time are perfectly fine as far as the timing jitter is under control.

Most XO stability tests are done through the rising edge of the signal so it's not a surprise to see worse jitter performance on the falling edges; the circuit inside XO is mostly not symmetric anyway. However, does this really matter?

[finneybear]

BTW, Elso, have you ever received the conversion boards yet? I am wondering if they got lost somewhere across Atlantic.

[Elso Kwak]

Originally posted by finneybear
BTW, Elso, have you ever received the conversion boards yet? I am wondering if they got lost somewhere across Atlantic.

Hello Finneybear,
Upon receipt of the boards I immediately wrote you an email to thank you. Apparently the email never did make it but the boards did. Thanks again!

[Niklas]

Hi guys!

You say falling edge usually look worse than rising edge.
I must say my falling edge looks better then my rising in a jitter type of view. I must say i am pretty unexperienced with digital clock signal so maybe i am wrong.

Though, using my tektronix scope with Instavu, I get a more "spread out" rising edge, and a very thin falling edge. From that i draw the conclusion that the rising edge is more jittery (made up word maybe??).
As far as i know the sampling instant must vary much more for a slow rise time than for a very fast one.

I will try to get a print out to illustrate what i try to explain, a picture says more than 1000 words =).


//Niklas

[Guido Tent]

Originally posted by finneybear
Now this is interesting. Which audio DAC is working on the falling edge of clock? Just curious. Most modern DACs have OSC inside synched with the external reference clock. It's odd that the internal OSC would synch with falling edges.

Anyway, rising edge, falling edge, the 2ns and 6ns setup time are perfectly fine as far as the timing jitter is under control.

Most XO stability tests are done through the rising edge of the signal so it's not a surprise to see worse jitter performance on the falling edges; the circuit inside XO is mostly not symmetric anyway. However, does this really matter?

Hi

What do you mean with " the internal OSC" ?

I do not remember the DAC converting at falling edge, it was many years ago

Why would an XO have worse specs at falling edge ?

To end with, I measure my clocks at bothe edges. And yes, the duty cycle does not matter that much, it is the timing variation of th edge used for conversion....

cheers

[machinow]

Originally posted by Elso Kwak

Hi Niklas, Don't worry too much. The ringing may be due to the measuring setup. Even the duty cycle adjustment is not critical as only the rising edge is used by then CDP.

YES, I experience similar ringing differences, but they are due to the scope probe /the ringings/ and due to different slew rate /the difference between rise/fall/
If a short 50 ohm coax cable is used to connect directly to the scope, and the 50 ohm resistor at the output IS present, no ringing can be seen. At least in my setup, AD8611 and AD8561 devices /the first one has higher SR/lower tranzition time/, double-layer PCB, 100nF+10nF decoupling next to the chip etc.
The circuit is great /and simple /
Regards