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Old 14th August 2002, 10:20 PM   #21
guido is offline guido  Netherlands
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Hi,

Going to use it for two TDA1541's. And i am going to connect the circuit to the decoder in my ancient cd player (SAA7210). It was all 16 bit in those days ;->

Actually, the service manual says saa7210, but in reality it is an M 4804 A 0041 LGH 8631 ???? Never found out what it is. It is one of the first players to use the 7210/7220/1541 chipset.

So two 16 bit (=4 8bit) are going to do the trick for me, but if you have more bits, you might have to use six 8 bit registers. i2s is flexible here.

I am going to use the GAL in registered mode, so all the outputs are clocked at the same time by the bitclock. It may depend on how sensitive the DAC is to the timing.. Guess it becomes more critical at oversampling (or feed two oversamplingfilters :-)

Anyway, first i'lll try something and if it works, i'll place a post.

Greetings,

Guido
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Old 15th August 2002, 02:55 AM   #22
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The size of the shift register varies with the length and polarity of the the frame. With the usual 32 bits per channel you need a 64 bit shift register for the +L and +R frames and a 96 bit shift register for the -L and -R frames. On semi make the MC14562 dual 128 bit shift register with taps at 32 bit intervals in a 14pin dil package.

ray.
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Old 15th August 2002, 10:31 AM   #23
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Thanks for the hint with the 4562. At 44.1 kHz with 32 bit frames, the clock will run at 2.8 MHz which is too much for a CMOS part at 5V. It may be necessary to run it at 10 or 15V and use level shifters.

There is a 4557 64 bit variable length register. Philips makes a metal gate version HEF4557BP that is a little faster.

Anybody looked into the 74HC40105 4 bit x 16 FIFO? Might be a complicated way to solve the problem at hand, but one could implement some jitter attenuation.

Eric
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Old 15th August 2002, 11:26 AM   #24
guido is offline guido  Netherlands
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Ok, ok,

This is my idea:

The WS signal tells the DAC when the new sample starts and when the second frame in the sample starts for the other channel.
Don't know by heart if left or right is first in and if WS if first high or low. Sorted this at home, but suppose it is like this:
I took 8 bit as example:

WS 1111111100000000
data LLLLLLLL RRRRRRRR

If we now invert WS, the DAC thinks the frame starts when the right channel is on the dataline, we can clock this into the right DAC:

WS 0000000011111111
data RRRRRRRR

So when WS changes to 1, we need also the left channel, but the first bit was there 16 clocktimes earlier. So I use a 16 bit shiftregister to delay it 16 clocktimes (output 7210 is 16 bit).

WS 0000000011111111
dataR RRRRRRRR
dataL LLLLLLLL

For the second frame of the sample, we need to have both frames delayed. But right is on the incoming dataline and is going into the same shiftregister as the left frame earlier. So we can use the output from the shiftregister again, but now the output should go to dataR. The left channel is delayed again by a second 16 bit shiftregister.

WS 000000001111111100000000
dataR RRRRRRRRRRRRRRRR
dataL LLLLLLLL LLLLLLLL

The GAL now sorts out when to put the 3 incoming datastreams (reall-time, 16 bit delayed and 32 bit delayed) on the lines dataR and dataL. Also using registered mode, so the output I2S is clocked (by the inverted incoming clock). So all the incoming signals have half the clocktime to settle.

And i have three mode-pins defined, for some extra features:
- Mute: dataR and dataL to zero
- Invert phase: dataR and dataL are the inverted from the
inputdata
- Differential: the second frame in the sample is inverted, so you
can use the DAC in balanced mode!

Easy with a GAL, just some programming.

Without the extra features, she circuit can be build with only some logic!

So 1 GAL and two 16 bit shift registers. I am going to use a 20V8 GAL for testing and 74HCT166 shiftregisters. I have these lying around, that's why. For higher bitrates, the 16 bit shifregisters can be changed for 24 bit or so. It should still work.

Going to try the above in the near future, keep you posted.

Any holes in my story ??

Greetings,

Guido
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Old 15th August 2002, 11:31 AM   #25
guido is offline guido  Netherlands
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Mmm,

I doesn't look like i intended, so load the text in an editor and
the timing-examples should look like this:

First: OK
Second: the datasignal RRRRRRRR should start under at the first 1 of the WS signal.
Third: both datasignals should start when WS changes from 0 to 1.
Fourth: both datasignals should start when WS changes from 0 to 1.

Hope this makes more sence.

Greetings,

Guido
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Old 15th August 2002, 03:07 PM   #26
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The only hole I can see is making something which is not 24 bits to start with

We are audiophiles, and should not do great design work for obsolesence. Does it help if you limit yourself to I2S out?

Petter
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Old 15th August 2002, 04:20 PM   #27
guido is offline guido  Netherlands
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Petter

I am not going to start a discusson here on which DAC is best, new old, non-os or os, 16 bit or 24 bit. Have some 1541's lying around and some people think old does not mean bad. But the I2S spec used nowadays for nearly all dacs does not specify the number of bits to be fixed to 16.

So the above works for 16, 18, 24 or more bits. The only change needed is that the shiftregisters should be adapted to this.
If the TDA was 24 bits, i would use 6 '166 registers to get two times 24 bit delay.

Therefore it might also be revant for the dac, the post was started for. I read that it can be configured to do all of the above internally by programming it with a serial port. If i was building a dac with two of those AD's, i would use that anyway. It would mean that only 1 chip is needed (pic-micro or so) and not 5.

I'll stop now poluting this thread and post a new one if there is new development.

Guido
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Old 16th August 2002, 02:24 PM   #28
tiroth is offline tiroth  United States
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Quote:
Originally posted by Petter
I too am sceptical to Iref volume settings. As I recall, the data sheet indicates that Iref variations is a way to change output volume, this is not however recommended for at least 2 reasons: 1. Reducing the Iref reduces the "effect" of each bit (my preferred method is to do this AFTER getting maximal utilization of every bit
2. The DAC is actually optimized for a specific current. Changing this current (be it increasing or decreasing), the performance will also suffer.
Petter
While this is far from laying the issue to rest, here is an encouraging Q&A from an Analog engineer:

Q. Could you comment on the relationship between IREF and the AD1853's THD and S/N figures as IREF is decreased from 1mA? The datasheet indicates attenuation to -50dB is possible via this method, but how much attenuation is possible before a significant increase in THD or S/N?

A. I have no actual data on this. Theoretically, as the bias current is decreased, the THD will improve somewhat as the current sources stay more in their linear region and for every 6dB decrease in gain the DNR will go down (get worse) by 3dB (the noise will decrease by 3dB). Referenced to full scale, the SNR will appear to improve by 3dB (limited by I/V noise).

------------
This was pretty much what I was hoping to hear.
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Old 16th August 2002, 03:33 PM   #29
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Yup, that was my feeling what was going to happen. We should not worry too much about dynamic range, it simply does not matter whether we have the noise at -90, -100 or -110 dB. And if disto decreases, that should be good...
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Old 16th August 2002, 11:48 PM   #30
guido is offline guido  Netherlands
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Hi,

Just to shoot at my own post. I did not work as i thought it would. Guess Ray (and others) already knew. A sample for one channel is 32 bit long, only the first 16 bit are used. Actually the MSB does not start at WS change, bit one clock periode later. I should read the datasheets better (that is, look at the correct picture)......

So i need two 32 bit registers. I have plenty of '166 lying around, so i'll 'piggy pack' four on top of the existing ones and create extra delay. Guess it all depends on the source. Could be that a 24 bit design also uses 32 bit for one sample, with 8 bits not used. Still a matter of putting in the correct delay.

Worse is that the MSB is shifted: it means using WS to control the differential output is not possible. The other features-pins i have in mind (mute:data=0 and phase inv: dataout=-datain) should work. But they are not important, the differential output is (to me).

I'll get there.

Greetings,

Guido
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