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Old 12th August 2002, 08:51 AM   #11
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It is hard to tell exactly without schematics, but here is a try from me. Please excuse me if these issues have already been adressed:

1. Is there an ADAT input still?

2. I am very pleased that you have added support for various types of IREF resistors and that the SRC's have been moved to the DAC daughter boards.

3. This may be sacrilege since I know how much emphasis you place on decoupling, but is there room for the following decoupling scenario Bypass Caps for digital IC decoupling
(see diagram) ref our participation in that thread?

4. I cannot see which regulators are used. Please advice.

Nice work!

Petter
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Old 12th August 2002, 02:11 PM   #12
tiroth is offline tiroth  United States
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Thanks for the compliments and the feedback Petter...I know this won't address all your questions but I am working on it. Okay, here is a boardshot in PDF format that is actually readable.

http://www.anidian.com/audio/pdf/boardshot.pdf

U7 (top SSOP) AD1853
U2 (mid SSOP) AD1896
U106 (bot SSOP) DIR1701 (or DIR1703)

The unidentifiable chip to the left of the reciever is an AD8561 (or LT1016) comparator. The network in the bottom right is the high-frequency (28MHz+) clock for AD1896. The network in the upper right is the divider and buffer network that generates MCK (24.576MHz), BCK, and LRCK.

Regulators are LT1762 (positive, <20uV noise) and LT1964 (negative, <30uV noise).

The ADAT reciever has disappeared, but will be back on its own board module. The reason for this was mainly cost (trying to maximize panel usage) and also flexibility. I wasn't sure many people would want the ADAT as designed...after all, the electrical interface wouldn't be compatible with off-the-shelf equipment. I may cook up two photo-etchable versions of the ADAT board...one for people like me, and one for "standard" usage.

Due to various considerations, I haven't duplicated ftorres' excellant bypassing work, but I have taken it into account as much as possible. Most of the bypassing is an 0805 right on the supply pad (intended to be 3.3uF stacked on 100nF) followed immediatly by 1210 (up to 22uF ceramic or tantalum) and a 100mil radial suitable for 220uF Panasonic FC or a more exotic cap. Regulators generally have 0805 pad at output and input and room for 680-1000uF FC at input, and are decoupled from the supply line by an inductor. Separate supply lines are run for analog and digital.

I've also updated all the schematic documents so you can get a pretty good idea of what the final design will be like. Check those out here:

http://www.anidian.com/audio/construct/adac_1.shtml
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Old 12th August 2002, 03:56 PM   #13
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AD1893 datasheet has a startup reset generator using ADM707, also from AD.

I think such autoreset might actually be worth it.

Petter
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Old 14th August 2002, 04:53 AM   #14
tiroth is offline tiroth  United States
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I have added ADM707 to the board, per AD datasheet and with manual reset (except with 4k7 series resistor on the reset line so that uP can control it). The board should be ready to run with or without external reset/controls.

This wraps up the board routing. I'll be doing some QA and hopefully send the design out to be fabbed in the next week or so. I'm still open to any suggestions or requests.
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Old 14th August 2002, 08:03 AM   #15
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Tiroth,

I'll be curious to hear how well your I_ref gain control circuit works.

I am sceptical about the benefit of using an upsampler, even if everybody is going crazy about those. What is the benefit of using an asynchronous upsampler compared to a more traditional integer digital filter? They both do the same thing, except that the asynchronous version has to use estimated (interpolated) coefficients to cope with ratios that are not a multiple of two. This cannot be more precise than using fixed and optimized coefficients.

It might be more beneficial to use the AD1853 in mono mode but I have not yet come up with a good idea for a compact code repeater that will copy the L signal into the slot for the R-channel data for one chip and vice versa for the other. Is there an FPGA wizard that can do this?

Eric
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Old 14th August 2002, 08:15 AM   #16
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capslock,

I gave Analog hell about this very issue a few years back. Last year, I also complained about their products requiring so much support circuitry.

If you look at the new "monster DAC", the AD1955, it has provisions for doing the L/R-->LL or RR internally. The problem with the 1955 though is that it needs to be programmed using a serial interface which is probably OK if you have a microprocessor but not if you don't. Thus, grafting in a 1955 will likely be easier than doing inversion.

I too am sceptical to Iref volume settings. As I recall, the data sheet indicates that Iref variations is a way to change output volume, this is not however recommended for at least 2 reasons: 1. Reducing the Iref reduces the "effect" of each bit (my preferred method is to do this AFTER getting maximal utilization of every bit
2. The DAC is actually optimized for a specific current. Changing this current (be it increasing or decreasing), the performance will also suffer.
I am not able to comment on the combined effect, however as I understand it the proposed layout has provisions for fixed resistor Iref ...

Petter
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Old 14th August 2002, 11:36 AM   #17
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Petter,

I am in fact not sceptical about the I_ref attenuation. With only 5 V supply, some parts of the analog circuitry are bound to operate near the rail limits, i.e. close to saturation. Attenuationg the currents a bit (not too much because then signal/noise suffers) might actually improve linearity. And after all, you don't really need all that dynamic range if you feed the DAC only with a 16 bit signal.

Eric
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Old 14th August 2002, 11:43 AM   #18
guido is offline guido  Netherlands
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Hi,

I am looking into the conversion from one i2s signal into two i2s signals, one with left channel and one with right channel data.

So i2s in with left/right to i2s with left/left and i2s with right/right data. I am working on a DAC with two TDA1541A's and would like to use the TDA's in mono mode. (Saw on Lesha's site that he has the same crazy (his words) idea).

I think i can do this by using two 16 bit shift registers (actually four 8 bit ones) and one 16V8 GAL. This is a predessor of the current CPLD logic stuff on the market.

Problem with the current stuff it that they are overkill for this,
>64 pin SMD etc. Also i already have a GAL programmer. Dropping some features and using normal logic should also work! With other words, i think a CPLD or GAL is not required, only some standards 74xx stuff.

I am going to test this with my old philips player, connecting one i2s signal to the original dac and one to a TDA1543 non-os dac i made to look into non os. See if the principle i had in mind works.

If it does, i'll start a post here, since it is standard i2s it should work for other dacs, even with oversampling (if the logic can keep up with the speed).

Greetings,

Guido
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Old 14th August 2002, 11:55 AM   #19
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Guido,

all the ideas I had involved 64 bits of shift registers and a bunch of other TTL functions but then I am not that experienced in digital logic design.

If you have a schematic for a smaller solution, just post it. I should be able to work out with pencil and paper what it does (or somebody with a simulator might be faster) - so there isn't even a need to build this.

Eric
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Old 14th August 2002, 09:01 PM   #20
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Surely you need 24 bit shift registers? I have seen some rather nice serial shift registers and guess it should be relatively easy to do this with discrete logic. I am not so sure about channel to channel timing, though ...

Petter
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