Some DAC thoughts

[Bernhard]

Hi,

1. maybe it is possible to manipulate the TDA1541 by connecting 100k pots with 1M resistors to Vdd, Vcc, and decouplig pins so that the voltage on each of the 14 pins can be adjusted.

2. use a >16bit parallel input DAC like PCM64 as a perfect 16bit DAC. Choose the input codes that match the desired output current, or even better the desired output voltage after I/V stage, burn it into an eprom.
But that needs a automated measuring system, no programming skills have I :-(

3. one DAC chip for each bit, test a batch of chips for perfect voltage matching codes of parallel input >16bit DACs and parallel them.
Much easier, just the question where to get those 32 PCM64.
Or use 16 bit DACs and test if any of the

4. How important is that a DAC sees exactly zero volts ?
Does it pay off to adjust input offset of I/V op amp ?

5.

[machinow]

You have the crazy idea
some thoughts:
- the overall performance will be /seriously/ limited by the measuring equipment that will be used. What will be the reference???
- serious amount of circuit, that may lead to noise and hum, and distortion too
- the overall cost appear to be quite high /but you can still choose to pay it /
But let me not discourage you, Bernhard, great inventions are peculiar to brave people and are preceded by "crazy" thoughts So go ahead and show us what your brain can do

[Bernhard]

For 1) a spectrum analyzer does the job, for 2) is a real problem, for 3) a 6 or 6 1/2 digit voltmeter, for 4 again a spectrum analyzer... If I had the time because of 5)

[machinow]

Ur idea leads me to this:
Feeding the first /say/ 8 MSBs to DAC No1.
Feeding the next 8-16 LSBs to DAC No2.
After I-V conersion, the 2 Voltage nodes sumes /with different coefficients/ and we have a true 16...24 bit DAC. The summer and I-V conversion should use multiple 1% or better resistors.
Digital data managment can be done by PLD or a discrete logic, you may find a friend to program the PLDs for you.

I suppose this is not a new idea, maybe in measurment equipment it is an usual stuff??? Similar things can be done with the sampling period/frequency too.

[machinow]

Excuse me, I was considering only 2- and 3- ideas

[Bernhard]

The problem is that accuracy of DAC No. 1 will not be sufficient.

[machinow]

Originally posted by Bernhard
The problem is that accuracy of DAC No. 1 will not be sufficient.

Why?? IF it converts 8 bits only and if it is a 16 bit DAC the non-linearity appears in the last 1 or max 2 LSBs. So I expect that a 16 bit DAC will have a true 8-bit linearity

[Bernhard]

But the error will be multiplied.
I have a datasheet of a R-2R ladder network IC somewhere, it is 4 bit and can be used to build 4, 8, or 12 bit dac. There are 3 grades, you need grades 1-3 for a 12 bit dac.

[lucpes]

I'd also like to know more about the input offset in an I/V stage (4 in Bernhard's post). Anyone?

[Lgrau]

I could imagine that the worst problem in calibration a DAC would be the drift because of temperature changes.

But if the dac was placed in a temperature controlled enviroment, it may be possible to do a calibration as you described. But again the self heating could destroy the calibration process.

I can't find any information on the PCM64 on TI's webpage, but if a calibration should be made, a 20/24bit dac should be used in order to calibrate the dac precise..

If there was no drift, the calibration could be done quite easy, by defining a stepsize for the lsb.

1. calibrate the LSB to the defined stepsize in both L & R DAC.

2. calibrate the output of LSBleftbit1-LSBrightbit0 to the defined stepsize.

3. calibrate LSBleftbit1-LSBrightbit1 to zero.

4. calibrate the output of LSBleftbit2 - (LSBrightbit1 + LSBrightbit0) to the defined stepsize.

5. calibrate LSBleftbit2-LSBrightbit2 to zero.

etc......

at the end it should be checked that all equal valued bit gives the same output, within a wanted value, and when increasing the input value to making a the next msb shift the stepsize is the defined stepsize.