PLL for CS8412/14 with dual switchable timeconstants

[ThorstenL]

Konnichiwa,

This is one thing I have been thinking about for a long time, but never quite got around to implementing a test.

We have two conflicting requirements for our PLL.

1) A turnover frequency for the PLL filter as low as possible to reject as much jitter as possible.

2) A turnover frequency for the PLL filter high enough to lock quickly.

The Datasheet suggests 1K/47nF for the filter.

I know some folks use much larger values for C and smaller values for R. Eventually the required locking will however happen very slowly and/or not at all, if the capacitor is too large.

So, how about this:

Normal WMS filter is employed, this locks quickly and fine.

An additional RC filter with 10 times (or even more) the Value for C and a corresponding lower R is placed, but it has additionally a Fet Switch to ground, bypassed with a resistor set to a 2 Second time constant with the capacitor.

In my example we would have 2.2uF in series with a 47R resistor from the FLT pin to a 1M resistor to ground.

The 1M resistor and the Capacitor form a 2 second time constant, meaning that within 2 seconds the voltage across our 2.2uF capacitor is always within 66% of the value of the stabilised PLL "pull" voltage. Within 10-15 seconds the voltage will settle to within a very small fraction of the average voltage on the PLL.

So, we connect a Switching FET across the 1M Resistor (a FET and not a relais to keep the layout tight) and 15 Seconds after the receivers "Lock" light goes on we trigger the FET, in effect moving the corner of the PLL Filter down another decade, from the approximatly 5KHz with 220nF/470R to around 500Hz.

We just need to make sure our FET switch opens the very instant "lock" is lost. If we want to be fancy we fit instead of the normal "lock" LED a multicolour one, including "blue" and select Red for "No Lock", Green for "Lock Aquired" and Blue for "Bliss"....

Has anyone actually ever tried this?

It might be fun doing that with a 22uF/4R7/100K combo to get a 50Hz PLL trunover point once the thing has locked....

Sayonara

[Jocko Homo]

Doing stuff like that usually makes for peaking in the recovered clock spectrum. And it doesn't really seem to reduce the jitter.

Jocko