AD1865N-K nos DIY

[ThorstenL]

Konnichiwa,

Originally posted by Elso Kwak
Hi Phippe, Put the opamp on the AD1865 chip out of service.

VERY EASY. Link Vout to SJ and leave Rf unconnected. Now Iout is your normal current out.

The Op-Amp now becomes a simple follower with it's input linked to ground....

Sayonara

[philbyx]

Hi Kuei Yang Wang,

VERY EASY. Link Vout to SJ and leave Rf unconnected. Now Iout is your normal current out.
The Op-Amp now becomes a simple follower with it's input linked to ground....

So simple that we didn't saw it!!!
Thank you.


Philippe

[Bricolo]

Thanks Elso & Thorsten

[philbyx]

Hi

I have started my new dac yesterday in the evening, and it works!!!!


The DAc is composed of :
PSU : +5 digital, +/-5 analog, +5 clock, +5 glue logic (74act74, 74act04)

A spdif transformer, made with a IBM 93 Ohms coax/110 Ohms twisted pair balun transformer.

1 cs8414 (with the filter cell = 3.3nf // with 470ohms-220nf).

A reclock stage : it reclocks the latch signal for the ad1865 with a guido tent low jitter oscillator.

2 ad8565 : it means 2 dacs/chanel : one for data, one for data inverted. Then balanced output for each chanel.

It works as I said at the beginning since yesterday.(just on resistors at the I output of the dacs).

I have to build the balanced U/I. I plan to build the Nelson DI U/I stage.


The drive is a ASUS CD-S520 (ASUS 52X CD-ROM). I take the Spdif signal, and I send the 33.8 MHz clock from the dac to the drive (from which I have extracted the poor ceramic oscillator).

Then all the components are synchronous and the spdif and drive jitter doesn't matter.

The fsync signal from the 8414 can shift + or - 7 ns, the reclocked Latch signal will allways be at time.

I'll prepare shematics for all of you

(I am waiting for your comments an critics)

Philippe

[wmincy]

hey Philippe,

Great work!!! Can you please post your dac schematic?? I'm quite interrested, hehe.

I got some AD1868, don't know if i can substituite with AD1865 or not. From the data sheet, they seem quite similar, and the signal input are same (LL, DL, CLK, LR, DR). I know it doesn't worth passing from AD1865 to AD1868. but it's just a test...

By the way, the problem occured on my dac, i found it and i think i'll have it fixed in these days, it was a defect of power supply!!!

Cheers

Mincy

[philbyx]

Hi Mincy

I'm happy for you : you solved your warm up problem.

I have to make the schematics of the Dac, but I only have Micro Cap simulator, and it is not the easier way to make logic diagrams.

Philippe

[philbyx]

The 1868 works in the same way for ll, lr, dl, dr and clock. LR and LL are the important signals as far as jitter is concerned, as for the ad 1865.
It is not the same pinout and you have only Vout (I is internal only).

Philippe

[philbyx]

Here is a schematic diagram which help to understand.
It's only the digital part.
I will post later the psus and the D1 (the wellknown...)

Philippe

[philbyx]

The +/-5V ana PSU

(The +5V dig PSU is the same but only one)

Philippe

[philbyx]

The +/- 30V for the D1 I/U converter

Philippe