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Old 26th December 2004, 12:48 AM   #1
jwb is offline jwb  United States
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Default Twinax, UTP, or STP for LVDS interconnect?

I need to pick an interconnect for my new project, which has the master clock, the digital input receiver, and the DAC all in separate chassis. So obviously I need to send the master clock to the CD Player, DVD player, DIR, and DAC, and I need an I2S link from the DIR to the DAC. All these are using LVDS signalling.

In the past I've used 3M MDR cable, which is cable with 13 individually-shielded twisted pairs. It is a 100Ω cable. I had some luck, because I was able to get these cables surplus. They are the same cables that were used for first-generation LCD computer displays, also called DFP cables. They are also sometimes called Cameralink cables. Anyway, the problem with these is the connectors are very expensive, and if you have to buy the cables new, it can be a fortune, up to $100 per meter, and difficult to find distances of less than 1 meter, and impossible to make the cables yourself without special tooling.

Another choice is twinaxial cable, like what use to be used in some IBM computer networks. This is another 100Ω cable, but i would probably need to buy 100 or 500 feet of cable and terminate it myself. PCB-mounted twinax connectors can also be hard to source. The primary drawback of twinaxial is I would need three cables for the I2S link.

Shielded twisted pair would work, as well as common unshielded networking cable. These are easy to source, cheap, easy to use, and I can build the cables myself. UTP might couple interference into the system, so I would stick with STP, most likely. The main objection to STP is the pairs are not individually shielded, so cross-talk may be an issue. [Note however that we can run gigabit and even 10 gigabit signals over twisted pair, so a proper implementation should ace the crosstalk test.]

A final option are VHDCI connectors and SCSI cables, but these have way more contacts than is called for (68, in fact), and are quite expensive.

I'm thinking of using STP for the clock links and MDR for the I2S. Your ideas and experiences with digital cabling would be appreciated.
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Old 26th December 2004, 03:02 AM   #2
gmarsh is offline gmarsh  Canada
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I'd say go with regular cat5/cat6 UTP and RJ45 jacks.

I'd be more worried about using shielded cable - adding extra ground connections between your boxes via the cable shields can open up all sorts of new possibilities for interference.

Though, using grounded RJ45 jacks lets you use either shielded or unshielded cable. If you run into problems, just change cable types.
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Old 26th December 2004, 10:29 AM   #3
JohnW is offline JohnW  Hong Kong
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JWB,

The first question I would ask is why is your Master Clock separated from the DAC? is an ADC involved?

As only the ADC / DAC require a low jitter clock, I would interconnect the units with cheapo optical cable - say 2nS random jitter. But this method would only work if the Master clock can be directly connected to the DAC / ADC section.

I used LVDS on a PCB design where the PCB track lengths where about 150mm on a well screened 4 layer PCB, and found the phase noise to be very poor. I even used a TDR system to optimize the termination - but with very little improvement.

Later, I built a "Test Jig" using high speed 400MHz "Single type" LVDS TX & RX noose to noose - no physical distance between them - with an ultra low phase noise clock and still measured 50pS – 100pS RMS short term phase noise.

LVDS is design for Comms systems which can tolerate Jitter up to 25% of operating frequency before Bit recovery rate goes out of Spec. Try to find Phase noise plots of LVDS from the manufactures...

I modified my PCB design to use UHS CMOS (Single Gate 5V) and achieved much lower phase noise results.

While this low level of phase noise might not be applicable to I2C signals it is important for the Master Clock – basically place the Clock as close as possible to the DAC / ADC.

John
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Old 26th December 2004, 04:39 PM   #4
jwb is offline jwb  United States
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Hi John, the reason for separating the functions is simply modularity. I want to be able to experiment with various DACs without having to discard the clock section. Also, since I will be doing multichannel DSP work, and my DACs are only 2-channel, I will be needing two or three DAC units, which all need to be clock-locked, and I also want the source and the DSP to be locked to the same frequency, so there's no need for an ASRC. So you can see why I want a separate clock.

The clock generator I want to use (AD9510 ) has significantly better performance when using the LVDS (or PECL) outputs than it does when using the CMOS outputs. That's why I want to keep everything in the LVDS domain.

I would imagine the phase noise performance of the LVDS transmission would depend very heavily on the power supply regulation of the transmitter. I'm planning to regulate the heck out of it, of course.
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Old 26th December 2004, 10:04 PM   #5
JohnW is offline JohnW  Hong Kong
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Hi JWB,

Had a quick look at the AD9510 Data sheet – seems like an interesting device – good to see Phase noise plots – at least for the driver outputs. They seem not to have published the PLL phase noise specs. – but then I guess you don’t plan to use the PLL section.

I’ve not used the AD part so cannot comment – but it seems like a good starting point – I guess.

The AD9510 will be used as the transmitter – but what LVDS receiver do you plan to use?

The test jig I used for the LVDS TX / RX test used ultra now noise regulators based upon LM5534 – with a well filtered Vref. FFT noise floor (16K points) was about -165dB Ref. 5V @ 10Hz.

I found LVDS to be EXREMALLY sensitive to cross coupling from fast CMOS edges – CMOS signals 2 -3inchs away would significantly couple into the LVDS signals.

To improve upon CMOS – I’ve gone to 5V PECL logic – but still don’t have full results. My first experience with PCEL was not promising either.

PECL logic has very low gain – and I didn’t appreciate the significant of “gain” in a digital system. But basically “gain” is what “Squares” slow moving edges – and thereby reducing “random” phase noise. PECL only has low phase noise when used with Fast edges – slow inputs result in high noise floors – poor wide band random phase noise.

Now I appreciate why PECL Crystal oscillator blocks are built with cascaded ECL gates - to increase the Gain of the oscillator section. Unlike CMOS logic, ECL logic with its low gain cannot be relied on to “Square” edges of slow input signals.

To this end, I never leave the “logic squaring” of a Crystal oscillator circuit to a HCU (un buffered Logic gate), but to a simple High Gain transistor amplifier stage – resulting in much lower wide band phase noise.

Slow moving inputs (as from a Sine wave input from an oscillator section) slowly transverse the logic transition point – from Low to High & High to Low. This slow transition allows a large “window of opportunity” as to when the gate will actually switch state – resulting in wide band random phase noise.

Also, a point to be aware of – with CMOS logic there’s a massive transient increase (for 1nS – 5nS) in input current as the gate transverses logic levels – I’ve measured more then 100mA (limited by the rise-time of the current probe I used). If the input is driven by a current limited source, then this will increase the transition time due to current starvation at the switching point – again increasing the “window of logic state opportunity” = increase random phase noise = high noise floor.

However, some system sound MUCH better with increased random phase noise due to its “Dither” effect!!! with audio it’s never safe to imply audio quality from measurements until all factors have been taken into consideration.

John
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Old 26th December 2004, 10:25 PM   #6
jwb is offline jwb  United States
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Thanks for the good info John. I'd love to see your test bench
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Old 27th December 2004, 02:48 AM   #7
jwb is offline jwb  United States
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Hi again John, let me throw another thought your way. You say "CMOS signals 2 -3inchs away would significantly couple into the LVDS signals." I agree, the problem is 5V CMOS signals couple into *everything*, at practically any distance. This is why LVDS seems attractive for a chassis-chassis interconnect, it won't interfere with anything (200mV p-p signalling, if I recall correctly).

The only other idea I had was to create extremely clean, 500mV p-p sine oscillators at the desired word clock frequencies (96kHz, 44.1kHz), distribute them on a balanced interconnect, and implement the local clocks in each piece of equipment with a multiplier and a clean PLL. Then I still have clock-locked operation, but I'm not trasmitting a 24.576MHz square wave outside the box. I would still use LVDS for the I2S link.

It sounds to me like you square your sines just by clipping a high-gain, high-speed amp. That sounds pretty good to me, but I wonder if there's a comparator out there with a small enough zero-crossing window to do the job properly.
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Old 27th December 2004, 07:52 AM   #8
JohnW is offline JohnW  Hong Kong
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JWB,

PECL & LVDS have the advantage that they are balanced signals so self emissions should cancel out. However they both have small signal swings – which reduce the S/N ratio.

To date, I’ve never seen a non Crystal based PLL which comes close to a good XO circuit. Even Crystal based PLL have loop filter spurs around the carrier – I would steer clear of PLL’s.

On cable runs of say 10cm or less, I would 5V CMOS and SMA/ SMB coax – large signal swings for good S/N – simple TX & RX. Drive with say dual gate Tiny logic 04’s series terminate for best overshoot / undershoot (output impedance of CMOS logic is not matched for High / Low logic states).

I guess a comparator is just a very high gain amplifier that’s happy to operate saturated. However while squaring “slow” signals - even with the best high speed ECL comparators I’ve only ever had the noise floor at around -130dBc 100Hz offset, hysterisis helps – but they still seem to bounce around a fair bit during transition – hard to beat a simple high gain amp if absolute transition point is not important.

John
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