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Old 19th December 2004, 09:41 AM   #1
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Default RE-clock for the TDA1541a non-oversampling DAC.

Dear all,

I was design two re-clock of the TDA1541a non-oversampling DAC. Test print also print out already.

Any comment for the re-clock can advise.

Pls ee the test print of the two re-clock in one PCB.

thx

thomas
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Old 19th December 2004, 10:21 AM   #2
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Exclamation Re: RE-clock for the TDA1541a non-oversampling DAC.

Quote:
Originally posted by tube-lover
Dear all,

I was design two re-clock of the TDA1541a non-oversampling DAC. Test print also print out already.

Any comment for the re-clock can advise.

Pls ee the test print of the two re-clock in one PCB.

thx

thomas
Hi Thomas,
A schematic of the reclock you envision would be more informative.
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Old 20th December 2004, 02:39 PM   #3
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Talking RE-clock for the TDA1541a non-oversampling DAC.

dear Elso Kwak,

I had two re-clock fit in one PCB. This is the schematic for one. any comment for this??

thx

thomas
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Old 20th December 2004, 03:17 PM   #4
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Question Re: RE-clock for the TDA1541a non-oversampling DAC./Schematic

Quote:
Originally posted by tube-lover
dear Elso Kwak,

I had two re-clock fit in one PCB. This is the schematic for one. any comment for this??

thx

thomas
Hello Thomas,
Did you attach a schematic to your post?
I did not see any scheme.
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Old 20th December 2004, 05:39 PM   #5
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yes, would it be nice to have that... post it
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Old 20th December 2004, 07:00 PM   #6
Bricolo is offline Bricolo  France
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Why 2 paralleled 431? I assume one is enough, those logic ICs certainly don't draw more than 100mA. Paralleling such low impedance shunts could cause more problems than solutions.

And, from what I've understood from the schematic, it only reclocks the bit clock (in fact, it's not reclocking but it creates a new bit clock)
why not reclocking the 3 (or 4) lines?
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Old 20th December 2004, 08:21 PM   #7
YENFU is offline YENFU  United States
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Default BUFFER RESISTORS

You could try to place a 100ohms resistor in series of the clock path.

The minor inductance of resistos will help to reduce the overshoot.
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Old 21st December 2004, 06:42 AM   #8
hifi is offline hifi  Sweden
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This method of reclocking is stolen from DDDAC. It works I have used it my self (for one TDA1543).

The main problem is it is not synchronous to the data stream so when the oscillator drifts you will either lose a sample or use the same one twice, when that happens the resulting jitter is ...

If I read the schematic correctly the tl431 shunts are not in parallell but one is for the oscillator and another for the 4040 divider.
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Old 21st December 2004, 06:55 AM   #9
hjelm is offline hjelm  Sweden
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IC8 and IC9 are parallel (IC10 and IC 11 also). I would not do that.
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Old 21st December 2004, 06:55 AM   #10
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Quote:
Originally posted by hifi
This method of reclocking is stolen from DDDAC. It works I have used it my self (for one TDA1543).

Imagine where is the other "taken" from ... that's why Elso jumped in.

Uncle Pedja already got a headache for such things... IMO if someone wants to make some boards for a original design he should at least inform the designer and give him credits (it would be better to ask him permission).

Cheers

Andrea
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